IEICE TRANSACTIONS on Fundamentals
Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Summary :
Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2519-2527
- Publication Date
- 2011/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.2519
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Level Design
Authors
Keyword
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Ce LI, Yiping DONG, Takahiro WATANABE, "Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 12, pp. 2519-2527, December 2011, doi: 10.1587/transfun.E94.A.2519.
Abstract: Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2519/_p
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@ARTICLE{e94-a_12_2519,
author={Ce LI, Yiping DONG, Takahiro WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture},
year={2011},
volume={E94-A},
number={12},
pages={2519-2527},
abstract={Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.},
keywords={},
doi={10.1587/transfun.E94.A.2519},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2519
EP - 2527
AU - Ce LI
AU - Yiping DONG
AU - Takahiro WATANABE
PY - 2011
DO - 10.1587/transfun.E94.A.2519
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.
ER -
English
