IEICE TRANSACTIONS on Fundamentals
A High Efficiency Hybrid Step-Up/Step-Down DC-DC Converter Using Digital Dither for Smooth Transition
Summary :
This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2685-2692
- Publication Date
- 2011/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.2685
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Circuit Design
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yanzhao MA, Hongyi WANG, Guican CHEN, "A High Efficiency Hybrid Step-Up/Step-Down DC-DC Converter Using Digital Dither for Smooth Transition" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 12, pp. 2685-2692, December 2011, doi: 10.1587/transfun.E94.A.2685.
Abstract: This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2685/_p
Copy
@ARTICLE{e94-a_12_2685,
author={Yanzhao MA, Hongyi WANG, Guican CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High Efficiency Hybrid Step-Up/Step-Down DC-DC Converter Using Digital Dither for Smooth Transition},
year={2011},
volume={E94-A},
number={12},
pages={2685-2692},
abstract={This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.},
keywords={},
doi={10.1587/transfun.E94.A.2685},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A High Efficiency Hybrid Step-Up/Step-Down DC-DC Converter Using Digital Dither for Smooth Transition
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2685
EP - 2692
AU - Yanzhao MA
AU - Hongyi WANG
AU - Guican CHEN
PY - 2011
DO - 10.1587/transfun.E94.A.2685
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.
ER -
English
