This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.

This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.

In many radio frequency identification (RFID) applications, the reader identifies the tags in its scope repeatedly. For these applications, many algorithms, such as an adaptive binary splitting algorithm (ABS), a single resolution blocking ABS (SRB), a pair resolution blocking ABS (PRB) and a dynamic blocking ABS (DBA) have been proposed. All these algorithms require the staying tags to reply with their IDs to be recognized by the reader. However, the IDs of the staying tags are stored in the reader in the last identification round. The reader can verify the existence of these tags when identifying them. Thus, we propose an anti-collision algorithm with short reply for RFID tag identification (ACSR). In ACSR, each staying tag emits a short reply to indicate its continued existence. Therefore, the data amount transmitted by staying tags is reduced significantly. The identification rate of ACSR is analyzed in this paper. Finally, simulation and analysis results show that ACSR greatly outperforms ABS, SRB and DBA in terms of the identification rate and average amount of data transmitted by a tag.