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MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.1 pp.324-331

- Publication Date
- 2011/01/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E94.A.324

- Type of Manuscript
- PAPER

- Category
- VLSI Design Technology and CAD

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

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Shingo YOSHIZAWA, Hirokazu IKEUCHI, Yoshikazu MIYANAGA, "VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 44 MIMO-OFDM Receiver" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 1, pp. 324-331, January 2011, doi: 10.1587/transfun.E94.A.324.

Abstract: MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.324/_p

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@ARTICLE{e94-a_1_324,

author={Shingo YOSHIZAWA, Hirokazu IKEUCHI, Yoshikazu MIYANAGA, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 44 MIMO-OFDM Receiver},

year={2011},

volume={E94-A},

number={1},

pages={324-331},

abstract={MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.},

keywords={},

doi={10.1587/transfun.E94.A.324},

ISSN={1745-1337},

month={January},}

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TY - JOUR

TI - VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 44 MIMO-OFDM Receiver

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 324

EP - 331

AU - Shingo YOSHIZAWA

AU - Hirokazu IKEUCHI

AU - Yoshikazu MIYANAGA

PY - 2011

DO - 10.1587/transfun.E94.A.324

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E94-A

IS - 1

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - January 2011

AB - MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.

ER -