IEICE TRANSACTIONS on Fundamentals
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions
Summary :
Accelerator cores in low-power embedded processors have on-chip multiple memory modules to increase the data access speed and to enable parallel data access. When large functional units such as multipliers and dividers are used for addressing, a large power and chip area are consumed. Therefore, recent low-power processors use small functional units such as adders and counters to reduce the power and area. Such small functional units make it difficult to implement complex addressing patterns without duplicating data among multiple memory modules. The data duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to reduce the memory duplication for window-based image processing, which is widely used in many applications. Evaluations using an accelerator core show that the proposed method reduces the data amount and data transfer time by more than 50%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.1 pp.342-351
- Publication Date
- 2011/01/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.342
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, "Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 1, pp. 342-351, January 2011, doi: 10.1587/transfun.E94.A.342.
Abstract: Accelerator cores in low-power embedded processors have on-chip multiple memory modules to increase the data access speed and to enable parallel data access. When large functional units such as multipliers and dividers are used for addressing, a large power and chip area are consumed. Therefore, recent low-power processors use small functional units such as adders and counters to reduce the power and area. Such small functional units make it difficult to implement complex addressing patterns without duplicating data among multiple memory modules. The data duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to reduce the memory duplication for window-based image processing, which is widely used in many applications. Evaluations using an accelerator core show that the proposed method reduces the data amount and data transfer time by more than 50%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.342/_p
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@ARTICLE{e94-a_1_342,
author={Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions},
year={2011},
volume={E94-A},
number={1},
pages={342-351},
abstract={Accelerator cores in low-power embedded processors have on-chip multiple memory modules to increase the data access speed and to enable parallel data access. When large functional units such as multipliers and dividers are used for addressing, a large power and chip area are consumed. Therefore, recent low-power processors use small functional units such as adders and counters to reduce the power and area. Such small functional units make it difficult to implement complex addressing patterns without duplicating data among multiple memory modules. The data duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to reduce the memory duplication for window-based image processing, which is widely used in many applications. Evaluations using an accelerator core show that the proposed method reduces the data amount and data transfer time by more than 50%.},
keywords={},
doi={10.1587/transfun.E94.A.342},
ISSN={1745-1337},
month={January},}
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TY - JOUR
TI - Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 342
EP - 351
AU - Hasitha Muthumala WAIDYASOORIYA
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2011
DO - 10.1587/transfun.E94.A.342
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2011
AB - Accelerator cores in low-power embedded processors have on-chip multiple memory modules to increase the data access speed and to enable parallel data access. When large functional units such as multipliers and dividers are used for addressing, a large power and chip area are consumed. Therefore, recent low-power processors use small functional units such as adders and counters to reduce the power and area. Such small functional units make it difficult to implement complex addressing patterns without duplicating data among multiple memory modules. The data duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to reduce the memory duplication for window-based image processing, which is widely used in many applications. Evaluations using an accelerator core show that the proposed method reduces the data amount and data transfer time by more than 50%.
ER -
English
