This paper proposes route advertisement policies (RAP) and an inbound traffic engineering (ITE) technique for a multihomed autonomous system (AS) employing the Border Gateway Protocol (BGP) and provider aggregatable (PA) addressing. The proposed RAP avail the advantage of address aggregation benefit of PA addressing. If multiple address spaces are allocated to each of the ASes that are multihomed to multiple upstream ASes, reduction of the forwarding information base (FIB) and quick convergence are achieved. However, multihoming based on PA addressing raises two issues. First, more specific address information is hidden due to address aggregation. Second, multiple allocated address spaces per AS does not provide the capability of ITE. To cope with these two limitations, we propose i) RAP to ensure connectivity among ASes with fewer routes installed in the FIB of each top-tier AS, and ii) an ITE technique to control inbound routes into multihomed ASes. Our ITE technique does not increase the RIB and FIB sizes in the Internet core. We implement the proposed RAP in an emulation environment with BGP using the Quagga software suite and our developed Hierarchical Automatic Number Allocation (HANA) protocols. We use HANA as a tool to automatically allocate hierarchical PA addresses to ASes. We confirm that with our proposed policies the FIB and RIB (routing information base) sizes in tier-1 ASes do not change with the increase of tier-3 ASes, and the number of BGP update messages exchanged is reduced by up to 69.9% from that achieved with conventional BGP RAP. We also confirmed that our proposed ITE technique, based on selective prefix advertisement, can indeed control inbound traffic into a multihomed AS employing PA addressing.

This letter presents a novel memory-based architecture for radix-2 fast Walsh-Hadamard-Fourier transform (FWFT) based on the constant geometry FWFT algorithm. It is composed of a multi-function Processing Engine, a conflict-free memory addressing scheme and an efficient twiddle factor generator. The address for memory access and the control signals for stride permutation are formulated in detail and the methods can be applied to other memory-based FFT-like architectures.

Accelerator cores in low-power embedded processors have on-chip multiple memory modules to increase the data access speed and to enable parallel data access. When large functional units such as multipliers and dividers are used for addressing, a large power and chip area are consumed. Therefore, recent low-power processors use small functional units such as adders and counters to reduce the power and area. Such small functional units make it difficult to implement complex addressing patterns without duplicating data among multiple memory modules. The data duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to reduce the memory duplication for window-based image processing, which is widely used in many applications. Evaluations using an accelerator core show that the proposed method reduces the data amount and data transfer time by more than 50%.

The current Internet is not capable of meeting the future communication requirements of society, i.e., reliable connectivity in a ubiquitous networking environment. The shortcomings of the Internet are due to the lack of support for mobility, multihoming, security and heterogeneous network layer protocols in the original design. Therefore, to provide ubiquitous networking facilities to the society for future innovation, we have to redesign the future Internet, which we call the New Generation Network. In this paper, we present the Heterogeneity Inclusion and Mobility Adaptation through Locator ID Separation (HIMALIS) architecture for the New Generation Network. The HIMALIS architecture includes a new naming scheme for generating host names and IDs. It also includes a logical control network to store and distribute bindings between host names, IDs, locators and other information useful for providing support for network operation and control. The architecture uses such information to manage network dynamism (i.e., mobility, multihoming) and heterogeneity in network layer protocols. We verify the basic functions of the architecture by implementing and testing them using a testbed system.

Multicast delivery in heterogeneous wireless networks requires careful coordination, in order to take full advantage of the resources such an interworking network environment can offer. Effective coordination, however, may require interworking signaling from coordinating network entities to receivers of a multicast service. Scalable delivery of such signaling is of great importance, since a large number of receivers may be interested in a multicast service. This paper therefore investigates the use of a multicast signaling channel (MSCH) to carry such interworking signaling in a scalable manner. Applications of interworking signaling for multicast service delivery in heterogeneous wireless networks are presented, motivating the need for an MSCH. Then a comparative study is performed analysing potential benefits of employing an MSCH for signaling message delivery compared to conventional unicast signaling. The analysis reveals that the benefits of the MSCH depend mainly on the selection of an appropriate signaling network to carry the MSCH and also on efficient addressing of a subset of receivers within the MSCH. Based on the findings, guidelines for the selection of a suitable signaling network are provided. Furthermore a novel approach is proposed that allows efficient addressing of a subset of receivers within a multicast group. The approach minimizes the required signaling load on the MSCH by reducing the size of the required addressing information. This is achieved by an aggregation of receivers with common context information. To demonstrate the concept, a prototype of the MSCH has been developed and is presented in the paper.

A high-speed drive technique is introduced in which addressing is done by eliminating, instead of accumulating, the wall charges. In the proposed scheme, wall charges are accumulated in all the cells in advance, and then the address discharges take place in selected cells to eliminate the wall charges. Sustain discharges are generated in these cells. In order to realize the proposed address scheme, re-designing of a setup waveforms was necessary. The data pulse of 1.33 µs wide and 84 V was realized in a Ne+10%Xe PDP. A contrast of 3,600:1 was obtained by providing one setup period in a TV field.

In this letter, a new addressing scheme for hexagonal networks is proposed. Using the new addressing scheme, many routing algorithms designed for networks using square-based topologies such as mesh and torus can also be applied to hexagonal networks. Methods of applying the turn model to hexagonal networks are derived, with some new minimal and partial adaptive routing algorithms obtained. Simulations of the new routing algorithms under different working conditions are carried on hexagonal networks of various sizes. The results show that the proposed algorithms can offer lower packet delay and loss rate than the popular dimension order routing algorithm.

A memory address allocation method for digital signal processors of indirect addressing with indexed auto-modification is proposed. At first, address auto-modification amounts for a given program are analyzed. And then, address allocation of program variables are moved and shifted so that both indexed and simple auto-modifications are effectively exploited. For further reduction in overhead codes, a memory address allocation method coupled with computational reordering is proposed. The proposed methods are applied to the existing compiler, and generated codes prove their effectiveness.

A simple address indexing method is proposed for path memory management in multi-PE Viterbi decoder, which solves data read/write conflict problem completely. This method not only simplifies control and addressing overhead but also has the advantage of requiring only two memory banks regardless of the number of PE's, with 100% PE utilization.

A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.

Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.

Digital signal processors (DSPs) usually employ indirect addressing using an address register (AR) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. In this paper, AR update scheme is extended such that address can be efficiently modified by 2 in addition to conventional 1 updates. An automatic address allocation method of program variables for this new addressing model is presented. The method formulates program variables and AR modifications by a graph, and extracts a maximum chained triangle graph, which is accessed only by AR 1 and 2 operations, so that the estimated number of overhead codes is minimized. The proposed methods are applied to a DSP compiler, and memory allocations derived for several examples are compared with memory allocations by other methods.

Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

In this paper, DSPs, of which memory addresses are pointed by special purpose registers (address registers: ARs), are assumed, and methods to derive an efficient memory access pattern for those DSPs proposed. In such DSPs, programmers must take care for efficient allocation of memory space as well as effective use of registers, in order to derive an efficient program in the sense of execution period. In this paper, memory addresses and AR update operations are modeled by an access graph, and a novel memory allocation method is presented. This method removes cycles and forks in a given access graph, and decides an address location of variables in memory space with less overhead. In order to utileze multiple ARs, methods to assign variables into ARs are investigated. The proposed methods are applied to the compiler for DSP56000 and are proved to be effective by generated codes for several examples.

Memory type polymer dispersed liquid crystal (PDLC) can be applied to a thermal addressing display device cell. Making use of its easy fabrication of large area display using flexible film substrate, the PDLC film can be used as reusable paper for direct-view mode display. In this study, memory type PDLC cells are prepared with an aluminum reflector deposited onto one side of the substrate and the reflection property in the PDLC cell with the reflector is clarified and compared to that without the reflector in the off-, on- and memory-states. The increase of contrast ratio and the decrease of driving voltage can be concurrently realized by decreasing the cell thickness by attaching the reflector. In addition, the reflected light in the off-state is bright and colorless due to the reflector, as compared with the weak, bluish reflected light in the cell without the reflector. Reflected light in the on-state and the memory-state are tinged with blue.

In this paper, the effects of the grouping and the addressing methods on the accuracy and the response time in a visual search task were investigated. Four grouping conditions (4, 8, 16 and 32 groups) and four addressing methods (random, ordered, cartesian and polar) were selected in the experiment. For each combination of grouping and addressing methods, subjects repeated the search task 30 times. No remarkable differences of the percent correct were observed both among the levels of grouping and among the addressing methods. The mean response time increased with the increase of the number of groups. Moreover, the interaction between addressing methods and grouping for both percent correct and response time was clarified.

A multi-valued addressing scheme is proposed for a high speed, high packing density memory system. This scheme is a level-multiplex addressing scheme instead of standard time-multiplex addressing scheme, and provides all address signals to the DRAM at the same time without increasing the address pin counts. This scheme makes memory matrix strechable and achieves the low power dissipation using the enhanced partial array activation. The 16 Mb stretchable memory matrix DRAM (16MbSTDRAM) is examined using this addressing design. A power dissipation of 121.5 mW, access time of 30 ns, and 20 pin have been estimated for 3.3 v 16MbSTDRAM with X/Y=15/9 adress configuration. The low power battery-drive memory system for such as the note-book or the handheld-type personal computers can be realized by the STDRAMs with the multi-valued addressing scheme.