A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
Summary :
We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2242-2250
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2242
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
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Junya KAWASHIMA, Hiroshi TSUTSUI, Hiroyuki OCHI, Takashi SATO, "A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2242-2250, December 2012, doi: 10.1587/transfun.E95.A.2242.
Abstract: We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2242/_p
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@ARTICLE{e95-a_12_2242,
author={Junya KAWASHIMA, Hiroshi TSUTSUI, Hiroyuki OCHI, Takashi SATO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits},
year={2012},
volume={E95-A},
number={12},
pages={2242-2250},
abstract={We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.},
keywords={},
doi={10.1587/transfun.E95.A.2242},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2242
EP - 2250
AU - Junya KAWASHIMA
AU - Hiroshi TSUTSUI
AU - Hiroyuki OCHI
AU - Takashi SATO
PY - 2012
DO - 10.1587/transfun.E95.A.2242
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.
ER -
English
