IEICE TRANSACTIONS on Fundamentals
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
Summary :
Caches are one of the most leakage consuming components in modern processor because of massive amount of transistors. To reduce leakage power of caches, several techniques using power-gating (PG) were proposed. Despite of its high leakage saving, a side effect of PG for caches is the loss of data during a sleep. If useful data is lost in sleep mode, it should be fetched again from a lower level memory. This consumes a considerable amount of energy, which very unfortunately mitigates the leakage saving. This paper proposes a new PG scheme considering data retentiveness of SRAM. After entering the sleep mode, data of an SRAM cell is not lost immediately and is usable by checking the validity of the data. Therefore, we utilize data retentiveness of SRAM to avoid energy overhead for data recovery, which results in further chance of leakage saving. To check availability, we introduce a simple hardware whose overhead is ignorable. Our experimental result shows that utilizing data retentiveness saves up to 32.42% of more leakage than conventional PG.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2301-2308
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2301
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
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Kyundong KIM, Seidai TAKEDA, Shinobu MIWA, Hiroshi NAKAMURA, "Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2301-2308, December 2012, doi: 10.1587/transfun.E95.A.2301.
Abstract: Caches are one of the most leakage consuming components in modern processor because of massive amount of transistors. To reduce leakage power of caches, several techniques using power-gating (PG) were proposed. Despite of its high leakage saving, a side effect of PG for caches is the loss of data during a sleep. If useful data is lost in sleep mode, it should be fetched again from a lower level memory. This consumes a considerable amount of energy, which very unfortunately mitigates the leakage saving. This paper proposes a new PG scheme considering data retentiveness of SRAM. After entering the sleep mode, data of an SRAM cell is not lost immediately and is usable by checking the validity of the data. Therefore, we utilize data retentiveness of SRAM to avoid energy overhead for data recovery, which results in further chance of leakage saving. To check availability, we introduce a simple hardware whose overhead is ignorable. Our experimental result shows that utilizing data retentiveness saves up to 32.42% of more leakage than conventional PG.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2301/_p
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@ARTICLE{e95-a_12_2301,
author={Kyundong KIM, Seidai TAKEDA, Shinobu MIWA, Hiroshi NAKAMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches},
year={2012},
volume={E95-A},
number={12},
pages={2301-2308},
abstract={Caches are one of the most leakage consuming components in modern processor because of massive amount of transistors. To reduce leakage power of caches, several techniques using power-gating (PG) were proposed. Despite of its high leakage saving, a side effect of PG for caches is the loss of data during a sleep. If useful data is lost in sleep mode, it should be fetched again from a lower level memory. This consumes a considerable amount of energy, which very unfortunately mitigates the leakage saving. This paper proposes a new PG scheme considering data retentiveness of SRAM. After entering the sleep mode, data of an SRAM cell is not lost immediately and is usable by checking the validity of the data. Therefore, we utilize data retentiveness of SRAM to avoid energy overhead for data recovery, which results in further chance of leakage saving. To check availability, we introduce a simple hardware whose overhead is ignorable. Our experimental result shows that utilizing data retentiveness saves up to 32.42% of more leakage than conventional PG.},
keywords={},
doi={10.1587/transfun.E95.A.2301},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2301
EP - 2308
AU - Kyundong KIM
AU - Seidai TAKEDA
AU - Shinobu MIWA
AU - Hiroshi NAKAMURA
PY - 2012
DO - 10.1587/transfun.E95.A.2301
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - Caches are one of the most leakage consuming components in modern processor because of massive amount of transistors. To reduce leakage power of caches, several techniques using power-gating (PG) were proposed. Despite of its high leakage saving, a side effect of PG for caches is the loss of data during a sleep. If useful data is lost in sleep mode, it should be fetched again from a lower level memory. This consumes a considerable amount of energy, which very unfortunately mitigates the leakage saving. This paper proposes a new PG scheme considering data retentiveness of SRAM. After entering the sleep mode, data of an SRAM cell is not lost immediately and is usable by checking the validity of the data. Therefore, we utilize data retentiveness of SRAM to avoid energy overhead for data recovery, which results in further chance of leakage saving. To check availability, we introduce a simple hardware whose overhead is ignorable. Our experimental result shows that utilizing data retentiveness saves up to 32.42% of more leakage than conventional PG.
ER -
English
