Unified Constant Geometry Fault Tolerant DCT/IDCT for Image Codec System on a Display Panel
Summary :
System-on-display panel design methodologies are proposed with the purpose of integrating DCT and IDCT on display panels for image codec and peripheral systems so as to reduce the bus data rate, memory size and power consumption. Unified constant geometry algorithms and architectures including recursive additions are proposed for DCT and IDCT butterfly computation, recursive additions and interconnections between stages. These schemes facilitate VLSI implementation and improve fault tolerance, suitable for low-yield SOP processing technologies through duplicate use of a PE as all the butterfly and recursive addition stages are composed and interconnected in a regular fashion. Efficient redundancy replacement methodologies optimizing the computation speed and the amount of hardware in various application areas are also described with testability and reliability issues. Finally, a performance analysis of speed, hardware and interconnection complexity is described with the proposed work's advantages.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2396-2406
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2396
- Type of Manuscript
- PAPER
- Category
- Digital Signal Processing
Authors
Keyword
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Jaehee YOU, "Unified Constant Geometry Fault Tolerant DCT/IDCT for Image Codec System on a Display Panel" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2396-2406, December 2012, doi: 10.1587/transfun.E95.A.2396.
Abstract: System-on-display panel design methodologies are proposed with the purpose of integrating DCT and IDCT on display panels for image codec and peripheral systems so as to reduce the bus data rate, memory size and power consumption. Unified constant geometry algorithms and architectures including recursive additions are proposed for DCT and IDCT butterfly computation, recursive additions and interconnections between stages. These schemes facilitate VLSI implementation and improve fault tolerance, suitable for low-yield SOP processing technologies through duplicate use of a PE as all the butterfly and recursive addition stages are composed and interconnected in a regular fashion. Efficient redundancy replacement methodologies optimizing the computation speed and the amount of hardware in various application areas are also described with testability and reliability issues. Finally, a performance analysis of speed, hardware and interconnection complexity is described with the proposed work's advantages.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2396/_p
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@ARTICLE{e95-a_12_2396,
author={Jaehee YOU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Unified Constant Geometry Fault Tolerant DCT/IDCT for Image Codec System on a Display Panel},
year={2012},
volume={E95-A},
number={12},
pages={2396-2406},
abstract={System-on-display panel design methodologies are proposed with the purpose of integrating DCT and IDCT on display panels for image codec and peripheral systems so as to reduce the bus data rate, memory size and power consumption. Unified constant geometry algorithms and architectures including recursive additions are proposed for DCT and IDCT butterfly computation, recursive additions and interconnections between stages. These schemes facilitate VLSI implementation and improve fault tolerance, suitable for low-yield SOP processing technologies through duplicate use of a PE as all the butterfly and recursive addition stages are composed and interconnected in a regular fashion. Efficient redundancy replacement methodologies optimizing the computation speed and the amount of hardware in various application areas are also described with testability and reliability issues. Finally, a performance analysis of speed, hardware and interconnection complexity is described with the proposed work's advantages.},
keywords={},
doi={10.1587/transfun.E95.A.2396},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Unified Constant Geometry Fault Tolerant DCT/IDCT for Image Codec System on a Display Panel
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2396
EP - 2406
AU - Jaehee YOU
PY - 2012
DO - 10.1587/transfun.E95.A.2396
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - System-on-display panel design methodologies are proposed with the purpose of integrating DCT and IDCT on display panels for image codec and peripheral systems so as to reduce the bus data rate, memory size and power consumption. Unified constant geometry algorithms and architectures including recursive additions are proposed for DCT and IDCT butterfly computation, recursive additions and interconnections between stages. These schemes facilitate VLSI implementation and improve fault tolerance, suitable for low-yield SOP processing technologies through duplicate use of a PE as all the butterfly and recursive addition stages are composed and interconnected in a regular fashion. Efficient redundancy replacement methodologies optimizing the computation speed and the amount of hardware in various application areas are also described with testability and reliability issues. Finally, a performance analysis of speed, hardware and interconnection complexity is described with the proposed work's advantages.
ER -
English
