System-on-display panel design methodologies are proposed with the purpose of integrating DCT and IDCT on display panels for image codec and peripheral systems so as to reduce the bus data rate, memory size and power consumption. Unified constant geometry algorithms and architectures including recursive additions are proposed for DCT and IDCT butterfly computation, recursive additions and interconnections between stages. These schemes facilitate VLSI implementation and improve fault tolerance, suitable for low-yield SOP processing technologies through duplicate use of a PE as all the butterfly and recursive addition stages are composed and interconnected in a regular fashion. Efficient redundancy replacement methodologies optimizing the computation speed and the amount of hardware in various application areas are also described with testability and reliability issues. Finally, a performance analysis of speed, hardware and interconnection complexity is described with the proposed work's advantages.

Low-temperature poly-Si thin film transistor with gate-overlapped LDD (GOLD) structure was fabricated. Reliability was evaluated using electrical stress method comparing conventional LDD and single drain structures. As previous researchers have reported, we have confirmed that the degradation of ON current and the field effect mobility was very small compared to conventional LDD or non-LDD structures. We have analyzed the reliability of the GOLD TFT using two-dimensional device simulator. We have clarified that vertical negative field plays a dominant role for improving the reliability in the GOLD TFT. Impact ionization occurs far from the interface between the oxide and poly-silicon by the vertical negative field. GOLD structure is promising for the realization of system on panel.