Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems
Summary :
We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.2 pp.550-558
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.550
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Shingo YOSHIZAWA, Yoshikazu MIYANAGA, "Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 2, pp. 550-558, February 2012, doi: 10.1587/transfun.E95.A.550.
Abstract: We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.550/_p
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@ARTICLE{e95-a_2_550,
author={Shingo YOSHIZAWA, Yoshikazu MIYANAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems},
year={2012},
volume={E95-A},
number={2},
pages={550-558},
abstract={We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.},
keywords={},
doi={10.1587/transfun.E95.A.550},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 550
EP - 558
AU - Shingo YOSHIZAWA
AU - Yoshikazu MIYANAGA
PY - 2012
DO - 10.1587/transfun.E95.A.550
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2012
AB - We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.
ER -
English
