IEICE TRANSACTIONS on Fundamentals
A Processor Accelerator for Software Decoding of Reed-Solomon Codes
Summary :
Decoding of Reed-Solomon (RS) codes requires many arithmetic operations in the Galois field. While the software decoding of RS codes has the advantage of its flexibility to support RS codes of variable parameters, the speed of the software decoding is slower than dedicated hardware RS decoders because arithmetic operations in the Galois field on an ordinary processor require many instruction steps. To achieve fast software decoding of RS codes, it is effective to accelerate Galois operations by both dedicated circuitry and parallel processing. In this paper, an accelerator is proposed which is attached to the base processor to speed up the software decoding of RS codes by parallel execution of Galois operations.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.5 pp.884-893
- Publication Date
- 2012/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.884
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kazuhito ITO, Keisuke NASU, "A Processor Accelerator for Software Decoding of Reed-Solomon Codes" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 5, pp. 884-893, May 2012, doi: 10.1587/transfun.E95.A.884.
Abstract: Decoding of Reed-Solomon (RS) codes requires many arithmetic operations in the Galois field. While the software decoding of RS codes has the advantage of its flexibility to support RS codes of variable parameters, the speed of the software decoding is slower than dedicated hardware RS decoders because arithmetic operations in the Galois field on an ordinary processor require many instruction steps. To achieve fast software decoding of RS codes, it is effective to accelerate Galois operations by both dedicated circuitry and parallel processing. In this paper, an accelerator is proposed which is attached to the base processor to speed up the software decoding of RS codes by parallel execution of Galois operations.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.884/_p
Copy
@ARTICLE{e95-a_5_884,
author={Kazuhito ITO, Keisuke NASU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Processor Accelerator for Software Decoding of Reed-Solomon Codes},
year={2012},
volume={E95-A},
number={5},
pages={884-893},
abstract={Decoding of Reed-Solomon (RS) codes requires many arithmetic operations in the Galois field. While the software decoding of RS codes has the advantage of its flexibility to support RS codes of variable parameters, the speed of the software decoding is slower than dedicated hardware RS decoders because arithmetic operations in the Galois field on an ordinary processor require many instruction steps. To achieve fast software decoding of RS codes, it is effective to accelerate Galois operations by both dedicated circuitry and parallel processing. In this paper, an accelerator is proposed which is attached to the base processor to speed up the software decoding of RS codes by parallel execution of Galois operations.},
keywords={},
doi={10.1587/transfun.E95.A.884},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - A Processor Accelerator for Software Decoding of Reed-Solomon Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 884
EP - 893
AU - Kazuhito ITO
AU - Keisuke NASU
PY - 2012
DO - 10.1587/transfun.E95.A.884
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2012
AB - Decoding of Reed-Solomon (RS) codes requires many arithmetic operations in the Galois field. While the software decoding of RS codes has the advantage of its flexibility to support RS codes of variable parameters, the speed of the software decoding is slower than dedicated hardware RS decoders because arithmetic operations in the Galois field on an ordinary processor require many instruction steps. To achieve fast software decoding of RS codes, it is effective to accelerate Galois operations by both dedicated circuitry and parallel processing. In this paper, an accelerator is proposed which is attached to the base processor to speed up the software decoding of RS codes by parallel execution of Galois operations.
ER -
English
