IEICE TRANSACTIONS on Fundamentals
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
Summary :
Capacitor charging modeling accelerates the time-domain simulation of power current of cryptographic VLSI circuits in a CMOS technology. The model finely represents the amount of charges consumed during the operation of Advanced Encryption Standard (AES) cores in a variety of logical implementations, reflecting their internal logical activities. This approach significantly reduces the complexity of power current simulation, and accomplishes acceleration by a factor of more than 200 over the traditional transistor-level circuit simulation. The correlated power analysis (CPA) attack against AES cores is successfully simulated with a conventional circuit simulator, with the models individually derived for 10,000 different cipher texts. The CPA is also experimentally performed against AES cores fabricated in a 65nm as well as 130nm CMOS technologies, using SASEBO measurement standards. The fast power current simulation is demonstrated to be accurate enough to evaluate the vulnerability of AES cores in various logical implementations as well as in different technologies, and exhibits general agreements with the silicon measurements.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2533-2541
- Publication Date
- 2013/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2533
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Daisuke FUJIMOTO
Kobe University
Toshihiro KATASHITA
National Institute of Advanced Industrial Science and Technology
Akihiko SASAKI
National Institute of Advanced Industrial Science and Technology
Yohei HORI
National Institute of Advanced Industrial Science and Technology
Akashi SATOH
The University of Electro-Communications
Makoto NAGATA
Kobe University
Keyword
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Daisuke FUJIMOTO, Toshihiro KATASHITA, Akihiko SASAKI, Yohei HORI, Akashi SATOH, Makoto NAGATA, "A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 12, pp. 2533-2541, December 2013, doi: 10.1587/transfun.E96.A.2533.
Abstract: Capacitor charging modeling accelerates the time-domain simulation of power current of cryptographic VLSI circuits in a CMOS technology. The model finely represents the amount of charges consumed during the operation of Advanced Encryption Standard (AES) cores in a variety of logical implementations, reflecting their internal logical activities. This approach significantly reduces the complexity of power current simulation, and accomplishes acceleration by a factor of more than 200 over the traditional transistor-level circuit simulation. The correlated power analysis (CPA) attack against AES cores is successfully simulated with a conventional circuit simulator, with the models individually derived for 10,000 different cipher texts. The CPA is also experimentally performed against AES cores fabricated in a 65nm as well as 130nm CMOS technologies, using SASEBO measurement standards. The fast power current simulation is demonstrated to be accurate enough to evaluate the vulnerability of AES cores in various logical implementations as well as in different technologies, and exhibits general agreements with the silicon measurements.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2533/_p
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@ARTICLE{e96-a_12_2533,
author={Daisuke FUJIMOTO, Toshihiro KATASHITA, Akihiko SASAKI, Yohei HORI, Akashi SATOH, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation},
year={2013},
volume={E96-A},
number={12},
pages={2533-2541},
abstract={Capacitor charging modeling accelerates the time-domain simulation of power current of cryptographic VLSI circuits in a CMOS technology. The model finely represents the amount of charges consumed during the operation of Advanced Encryption Standard (AES) cores in a variety of logical implementations, reflecting their internal logical activities. This approach significantly reduces the complexity of power current simulation, and accomplishes acceleration by a factor of more than 200 over the traditional transistor-level circuit simulation. The correlated power analysis (CPA) attack against AES cores is successfully simulated with a conventional circuit simulator, with the models individually derived for 10,000 different cipher texts. The CPA is also experimentally performed against AES cores fabricated in a 65nm as well as 130nm CMOS technologies, using SASEBO measurement standards. The fast power current simulation is demonstrated to be accurate enough to evaluate the vulnerability of AES cores in various logical implementations as well as in different technologies, and exhibits general agreements with the silicon measurements.},
keywords={},
doi={10.1587/transfun.E96.A.2533},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2533
EP - 2541
AU - Daisuke FUJIMOTO
AU - Toshihiro KATASHITA
AU - Akihiko SASAKI
AU - Yohei HORI
AU - Akashi SATOH
AU - Makoto NAGATA
PY - 2013
DO - 10.1587/transfun.E96.A.2533
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - Capacitor charging modeling accelerates the time-domain simulation of power current of cryptographic VLSI circuits in a CMOS technology. The model finely represents the amount of charges consumed during the operation of Advanced Encryption Standard (AES) cores in a variety of logical implementations, reflecting their internal logical activities. This approach significantly reduces the complexity of power current simulation, and accomplishes acceleration by a factor of more than 200 over the traditional transistor-level circuit simulation. The correlated power analysis (CPA) attack against AES cores is successfully simulated with a conventional circuit simulator, with the models individually derived for 10,000 different cipher texts. The CPA is also experimentally performed against AES cores fabricated in a 65nm as well as 130nm CMOS technologies, using SASEBO measurement standards. The fast power current simulation is demonstrated to be accurate enough to evaluate the vulnerability of AES cores in various logical implementations as well as in different technologies, and exhibits general agreements with the silicon measurements.
ER -
English
