IEICE TRANSACTIONS on Fundamentals
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages
Summary :
In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2597-2611
- Publication Date
- 2013/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2597
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
Authors
Shin-ya ABE
Waseda University
Youhua SHI
Waseda University
Kimiyoshi USAMI
Waseda University,Shibaura Institute of Technology,Waseda University
Masao YANAGISAWA
Waseda University
Nozomu TOGAWA
Waseda University
Keyword
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Shin-ya ABE, Youhua SHI, Kimiyoshi USAMI, Masao YANAGISAWA, Nozomu TOGAWA, "Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 12, pp. 2597-2611, December 2013, doi: 10.1587/transfun.E96.A.2597.
Abstract: In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2597/_p
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@ARTICLE{e96-a_12_2597,
author={Shin-ya ABE, Youhua SHI, Kimiyoshi USAMI, Masao YANAGISAWA, Nozomu TOGAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages},
year={2013},
volume={E96-A},
number={12},
pages={2597-2611},
abstract={In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.},
keywords={},
doi={10.1587/transfun.E96.A.2597},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2597
EP - 2611
AU - Shin-ya ABE
AU - Youhua SHI
AU - Kimiyoshi USAMI
AU - Masao YANAGISAWA
AU - Nozomu TOGAWA
PY - 2013
DO - 10.1587/transfun.E96.A.2597
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.
ER -
English
