IEICE TRANSACTIONS on Fundamentals
Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders
Summary :
The throughput rate of Viterbi decoding (VD) is not limited by the speed of functional units when look-ahead computation techniques are used. The disadvantages of the look-ahead computation in VD are the hardware complexity and the decode latency. In this paper, implementation methods of the look-ahead ACS computation are proposed to improve the hardware efficiency and reduce the latency where the hardware efficiency and the latency can be balanced with a single parameter.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2680-2688
- Publication Date
- 2013/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2680
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
Authors
Kazuhito ITO
Saitama University
Ryoto SHIRASAKA
Saitama University
Keyword
Latest Issue
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Kazuhito ITO, Ryoto SHIRASAKA, "Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 12, pp. 2680-2688, December 2013, doi: 10.1587/transfun.E96.A.2680.
Abstract: The throughput rate of Viterbi decoding (VD) is not limited by the speed of functional units when look-ahead computation techniques are used. The disadvantages of the look-ahead computation in VD are the hardware complexity and the decode latency. In this paper, implementation methods of the look-ahead ACS computation are proposed to improve the hardware efficiency and reduce the latency where the hardware efficiency and the latency can be balanced with a single parameter.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2680/_p
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@ARTICLE{e96-a_12_2680,
author={Kazuhito ITO, Ryoto SHIRASAKA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders},
year={2013},
volume={E96-A},
number={12},
pages={2680-2688},
abstract={The throughput rate of Viterbi decoding (VD) is not limited by the speed of functional units when look-ahead computation techniques are used. The disadvantages of the look-ahead computation in VD are the hardware complexity and the decode latency. In this paper, implementation methods of the look-ahead ACS computation are proposed to improve the hardware efficiency and reduce the latency where the hardware efficiency and the latency can be balanced with a single parameter.},
keywords={},
doi={10.1587/transfun.E96.A.2680},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2680
EP - 2688
AU - Kazuhito ITO
AU - Ryoto SHIRASAKA
PY - 2013
DO - 10.1587/transfun.E96.A.2680
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - The throughput rate of Viterbi decoding (VD) is not limited by the speed of functional units when look-ahead computation techniques are used. The disadvantages of the look-ahead computation in VD are the hardware complexity and the decode latency. In this paper, implementation methods of the look-ahead ACS computation are proposed to improve the hardware efficiency and reduce the latency where the hardware efficiency and the latency can be balanced with a single parameter.
ER -
English
