The throughput rate of Viterbi decoding (VD) is not limited by the speed of functional units when look-ahead computation techniques are used. The disadvantages of the look-ahead computation in VD are the hardware complexity and the decode latency. In this paper, implementation methods of the look-ahead ACS computation are proposed to improve the hardware efficiency and reduce the latency where the hardware efficiency and the latency can be balanced with a single parameter.

The letter presents an analysis of bit error probability for trellis coded 8-ary phase shift keying moduation with 2-state soft decision Viterbi decoding. It is shown that exact numerical error performance can be obtained for low singal-to-noise power ratio where bounds are useless.

This paper presents a new technique to implement a convolutional codec in VLSI. The code is used in the Trellis Code Modulation. The technique aims to reduce hardware complexity and increase throughput to decode the convolutional code using Viterbi algorithm. To simplify decoding algorithm and calculation, branch cost distances are pre-calculated and stored in a Distance Look Up Table (DLUT). By using the DLUT to get each branch cost in the algorithm, the hardware implementation of the algorithm does not require any calculation circuits. Furthermore, based on the trellis diagram, an Output Look-Up-Table (OLUT) is also constructed for decoding output generation. This table reduces the amount of storage in the algorithm. The use of look-up tables reduces hardware complexity and increases throughput of the decoder. Using this technique, a 16-states, radix-4 TCM codec with 2-D and 4-D was designed and implemented in both FPGA and ASIC after mathematically simulated. The tested ASIC has a core area of 1.1 mm2 in 0.18 µm CMOS technology and yields a decoding speed over 500 Mbps. Implementation results have shown that LUT can be used to decrease hardware requirement and to increase decoding speed. The designed codec can be used as an IP core to be integrated into system-on-chip applications and the technique can be explored to use to decode the turbo code.

Recently, space-time multiple trellis coded modulation (ST-MTCM) has been introduced in order to achieve maximum transmit diversity gain and larger coding gain with the existance of parallel paths, which can not be achieved with STTCM system. In order to achieve good performance, it is crucial to maximize the intra-distance, which is defined by parallel paths and determine the performance. Conventional ST-MTCM uses a generator matrix G for coded modulation; however, we find that no matrix can be designed which can maximize the intra-distance by computer search. In this paper, we focus on maximizing the intra-distance and the diversity gain, and hence design a new coded modulation scheme. We use trellis codes in this paper which cannot be described by a matrix G. The proposed codes can achieve the maximum intra-distance and thus good coding gain, which may not be achieved by conventional codes. We also show that the proposed code can achieve good performance both in quasi-static and fast flat fading channels without the need for changing the codes as is necessary in the conventional ST-MTCM scheme.

It is known that Viterbi decoding based on the code trellis and syndrome decoding based on the syndrome trellis (i.e., error trellis) are equivalent. In this paper, we show that Scarce State Transition (SST) Viterbi decoding of convolutional codes is equivalent to syndrome decoding. First, we derive fundamental relations between the hard-decision input to the main decoder and the encoded data for the main decoder. Then using these relations, we show that the code trellis module for the main decoder in an SST Viterbi decoder can be reduced to a syndrome trellis module. This fact shows that SST Viterbi decoding based on the code trellis is equivalent to syndrome decoding based on the syndrome trellis. We also calculate the SST Viterbi decoding metrics for general convolutional codes assuming an AWGN channel model. It is shown that the derived metrics are equal to those of conventional Viterbi decoding. This fact shows that SST Viterbi decoding is equivalent to conventional Viterbi decoding, and consequently to syndrome decoding.

This paper proposes a space division multiplexed - coded orthogonal frequency division multiplexing (SDM-COFDM) scheme for multi-input multi-output (MIMO) based broadband wireless LANs. The proposed scheme reduces inter-channel interference in SDM transmission with a simple feed-forward canceller which multiplies the received symbols by the estimated propagation inverse matrix for each OFDM subcarrier. This paper proposes a new preamble pattern in order to improve power efficiency in the estimation of the propagation matrix. Moreover, the proposed likelihood-weighting scheme, which is based on signal-to-noise power ratio (SNR) of each OFDM subcarrier, improves the error correction performance of soft decision Viterbi decoding. Computer simulation shows that the proposed SDM-COFDM scheme with two transmitting/receiving antennas doubles the transmission rate without increasing the channel bandwidth and achieves almost the same PER performance as the conventional single-channel transmission in frequency selective fading environments. In particular, it achieves more than 100 Mbit/s per 20 MHz by using 64QAM with the coding rate of 3/4.

In this letter, an analysis of bit error probability of 4-state soft decision Viterbi decoding is presented. The bit error probability of recursive systematic convolutional code is also derived.

Both Viterbi decoding with labels (i.e., the Yamamoto-Itoh scheme) and the soft-output Viterbi algorithm (SOVA) evaluate the metric difference between the maximum-likelihood (ML) path and the discarded path at each level in the trellis. Noting this fact, we show that the former scheme also provides information about the reliability values for decoded information bits.

We propose a soft decision Viterbi decoding scheme and a self-interference cancellation method applicable to a Parallel Combinatory CDMA (PC-CDMA) system. In this decoding scheme, branch metric is calculated for every bit by weighting the output levels of the PC-CDMA correlators so as to enable an effective soft decision capability to the system. The effectivity of this scheme is then further enhanced by the use of a simple pseudo-random bit interleaving scheme. Moreover, to increase the capacity of the PC-CDMA system, we propose a simple self-interference cancellation method for self-induced cross-correlation arising from the multipath environment. This further enhances the efficacy of the decoding scheme because the false contributions of the self-induced cross-correlation component are removed from the branch metric prior to soft decision Viterbi decoding. Finally, we simulated a possible PC-CDMA system with a user data rate of 1.92Mbps, transmitting it at a chip rate of 3.84Mcps and at 7.68Mcps under a multipath-Rayleigh fading interference environment. For a chip rate of 7.68Mcps, BER after Viterbi decoding is less than 3.2e-7 even without the use of interference cancellation. For a chip rate of 3.84Mcps, BER after Viterbi decoding with interference cancellation is 1.0e-4.

Viterbi decoding is known as a decoding scheme that can realize maximum likelihood decoding. However, it is impossible to continue it without re-synchronization even if only an insertion/deletion error occurs in a channel. In this paper, we show that Levenshtein distance is suitable for the metric of Viterbi decoding in a channel where not only symbol errors but also insertion/deletion errors occur under some conditions and we propose a kind of Viterbi decoding considering insertion/deletion errors.

The structure of an SST Viterbi decoder for general rate (n-1)/n convolutional codes is investigated in the light of syndrome decoding. Since the input to the main decoder is expressed as S(H-1)T (S: syndrome, H: dual encoder of G) for a general non-systematic convolutional code G if the inverse encoder G-1 is used as a pre-decoder, SST Viterbi decoding can be regarded as searching for the most likely error sequence through an extended syndrome trellis. We show that searching based on the extended syndrome trellis is equivalent to the original syndrome decoding by applying the invariant-factor theorem.

The performance of the hybrid-ARQ scheme with a convolutional code, in which the retransmission criterion is based on an estimated decoding error rate, is evaluated for moderately time-varying channels. It is shown by computer simulations that the simple average diversity combining scheme can almost attain the same performance as the optimally weighted diversity combining scheme. For the whole and partial retransmission schemes with the average diversity combining, the theoretical bounds of throughput and bit error rate are derived, and it is shown that their bounds are tight and the treated schemes can attain a given error rate with good throughput for moderately time-varying channels. Furthermore, the throughput is shown to be improved by the partial retransmission scheme compared with the whole retransmission scheme.

A new Hybrid-ARQ scheme with a convolutional code and the Viterbi decoding is proposed, which uses the packet combining technique and a retransmission criterion based on an estimated decoding error rate. The throughput and bit error rate are evaluated by theoretical bounds and computer simulations. It is shown that a given error rate tolerance can be attained with good throughput for any signal to noise ratio, i.e. for the slow time-varying channels. Furthermore, the throughput performance can be improved by retransmitting not all but a part of packet.

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communication systems. However, excessive time consumption makes it difficult to design an efficient high-speed decoder for practical application. This paper describes the implementation of parallel Viterbi algorithm by multi-microprocessors. Internal computations are performed in a parallel fashion. The use of microprocessors allows low-cost implementation with moderate complexity. The software and hardware implementations of the Viterbi algorithm on parallel multi-microprocessors for real-time decoding are presented. The implemented method is based on a combination of forming a set of tables and calculations. For efficient operation under fully parallel Viterbi decoding by microprocessors, we considered: (1) branch metrics processing, path metrics updating, path memory updating and decoding output for microprocessor, (2) efficient decomposition of the sequential Viterbi algorithm into parallel algorithms, (3) minimization of the communication among the microprocessors. The practical solutions for the problems of synchronization among the miroprocessors, interconnection network for communication among the microprocessors and memory management are discussed. Furthermore the performance and the speed of the parallel Viterbi decoding are given. For a fixed processing speed of given hardwares, parallel Viterbi decoding allows a linear speed up in the throughput rate with a linear increase in hardware complexity.

An optical On-Off Keyed (OOK) pulse is often stretched in dispersive channels, thus producing intersymbol interference (ISI) and degrading the performance. In this paper, error probability is presented for a convolutionally encoded optical OOK channels with ISI. Both ISI-matched and ISI-mismatched decoders are taken into account in the error probability analysis. The encoded optical OOK signal is received by Avalanche Photo Diode (APD) and the number of APD output photo-electrons is counted for soft decision Viterbi decoding. Error probability is derived for a 3-bit and an ideal soft decision schemes in ISI-mismatched decoder and for an ideal soft decision scheme in ISI-matched decoder. Numerical results demonstrate the effects of mismatching or 3-bit soft decision scheme. Some computer simulations are carried out to confirm the validity of the analysis.

In this paper, we study the performance of convolutional coding using an error-and-erasure correction Viterbi decoder for π/4-shift QDPSK mobile radio transmission. The receiver uses received signal envelope as channel state information to erase unreliable symbols instead of making explicit decision before decoding. The performance study is carried out over frequency-selective fading channel with additive white Gaussian noise, co-channel interference and propagation delay spread. The results show that decoding with symbol erasure can significantly improve the system transmission performance compared to decoding without symbol erasure.

In power line SS communication system, since available frequency range is limited from 10 kHz to 450 kHz by the law, we can't transmit any components of lower and higher frequency regions. In this paper, we propose a method for improving bit error rate by using the PN sequence coded by the new channel code, FM-V5 code, instead of PE code to have correlation property in the coded PN sequence. Correlation property in the coded PN sequence makes us effectively use Viterbi decoding technique on the receiving side. To enhance correlation property more, we also examine to apply additionally partial response (PR) system, so called PRML system, on the receiving side. The results of computer simulation show the improvement of about 4.5 dB on SNR at bit error rate 10-5 by using FM-V5 code without PR system compared with PE code. In the case of FM-V5 code with PR(1, -1) system, we get the further improvement of about 11 dB on SNR at the same bit error rate 10-5 compared with PE code. As a result, our method can attain SNR improvement about 20 dB compared with conventional simple PN sequence, that is the conventional Direct Sequence/Spread Spectrum (DS/SS), method.

The DSD (Double Soft Decision) concatenated forward error correction scheme is proposed to realize a higher-coding-gain forward error correction system with simple hardware. The novel scheme soft decision decodes inner codes as well as outer codes. In this scheme, likelihood information from an inner Viterbi decoder is used for the decoding of outer codes. Path memory circuit status 1,0 ratio is newly proposed as a measure of likelihood information and it is shown that this method is the most reliable even though it has the simplest hardware among the alternative likelihood information extracting methods. Computer simulation clarifies that the proposed DSD scheme improves Pe performance to one-third that of the conventional hard decision outer decoding.

A fast Viterbi decoding technique with path reduction in optical channels is presented. This decoding exploits the asymmetric characteristic of optical channels. In the decoding trellis, the branches with low or no possibility being correct path are eliminated based on the detected signal level. The number of Add-Compare-Select (ACS) operations which occupy the dominant part of Viterbi decoding is considerably reduced due to branch eliminations, and fast decoding is realized by decoding asynchronously to received sequence. The reduction of the number of ACS operations is derived for the codes with rate 1/2. It is shown that the number of ACS operations is considerably reduced compared with the conventional Viterbi decoding. The bit error probability of the proposed decoding is derived for noiseless photon counting channel. It is also shown that the decoding technique can be applied to the cases using avalanche photo diode (APD) based receiver with dark current noise at a cost of negligible degradation on the bit error probability.