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[Author] Anh DINH(4hit)

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  • A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips

    Trung Anh DINH  Shigeru YAMASHITA  Tsung-Yi HO  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E99-A No:2
      Page(s):
    570-578

    Different from application-specific digital microfluidic biochips, a general-purpose design has several advantages such as dynamic reconfigurability, and fast on-line evaluation for real-time applications. To achieve such superiority, this design typically activates each electrode in the chip using an individual control pin. However, as the design complexity increases substantially, an order-of-magnitude increase in the number of control pins will significantly affect the manufacturing cost. To tackle this problem, several methods adopting a pin-sharing mechanism for general-purpose designs have been proposed. Nevertheless, these approaches sacrifice the flexibility of droplet movement, and result in an increase of bioassay completion time. In this paper, we present a novel pin-count reduction design methodology for general-purpose microfluidic biochips. Distinguished from previous approaches, the proposed methodology not only reduces the number of control pins significantly but also guarantees the full flexibility of droplet movement to ensure the minimal bioassay completion time.

  • An Equalization Technique for 54 Mbps OFDM Systems

    Naihua YUAN  Anh DINH  Ha H. NGUYEN  

     
    PAPER-Communication Theory and Systems

      Vol:
    E87-A No:3
      Page(s):
    610-618

    A time-domain equalization (TEQ) algorithm is presented to shorten the effective channel impulse response to increase the transmission efficiency of the 54 Mbps IEEE 802.11a orthogonal frequency division multiplexing (OFDM) system. In solving the linear equation Aw = B for the optimum TEQ coefficients, A is shown to be Hermitian and positive definite. The LDLT and LU decompositions are used to factorize A to reduce the computational complexity. Simulation results show high performance gains at a data rate of 54 Mbps with moderate orders of TEQ finite impulse response (FIR) filter. The design and implementation of the algorithm in field programmable gate array (FPGA) are also presented. The regularities among the elements of A are exploited to reduce hardware complexity. The LDLT and LU decompositions are combined in hardware design to find the TEQ coefficients in less than 4 µs. To compensate the effective channel impulse response, a radix-4 pipeline fast Fourier transform (FFT) is implemented in performing zero forcing equalization. The hardware implementation information is provided and simulation results are compared to mathematical values to verify the functionalities of the chips running at 54 Mbps.

  • A New Implementation Technique to Decode the Convolutional Code in Trellis-Coded Modulation

    Anh DINH  Xiao HU  

     
    PAPER-Communication Theory and Systems

      Vol:
    E87-A No:3
      Page(s):
    619-627

    This paper presents a new technique to implement a convolutional codec in VLSI. The code is used in the Trellis Code Modulation. The technique aims to reduce hardware complexity and increase throughput to decode the convolutional code using Viterbi algorithm. To simplify decoding algorithm and calculation, branch cost distances are pre-calculated and stored in a Distance Look Up Table (DLUT). By using the DLUT to get each branch cost in the algorithm, the hardware implementation of the algorithm does not require any calculation circuits. Furthermore, based on the trellis diagram, an Output Look-Up-Table (OLUT) is also constructed for decoding output generation. This table reduces the amount of storage in the algorithm. The use of look-up tables reduces hardware complexity and increases throughput of the decoder. Using this technique, a 16-states, radix-4 TCM codec with 2-D and 4-D was designed and implemented in both FPGA and ASIC after mathematically simulated. The tested ASIC has a core area of 1.1 mm2 in 0.18 µm CMOS technology and yields a decoding speed over 500 Mbps. Implementation results have shown that LUT can be used to decrease hardware requirement and to increase decoding speed. The designed codec can be used as an IP core to be integrated into system-on-chip applications and the technique can be explored to use to decode the turbo code.

  • Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips

    Trung Anh DINH  Shigeru YAMASHITA  Tsung-Yi HO  Yuko HARA-AZUMI  

     
    PAPER-High-Level Synthesis and System-Level Design

      Vol:
    E96-A No:12
      Page(s):
    2668-2679

    Microfluidic biochips, also referred to “lab-on-a-chip,” have been recently proposed to integrate all the necessary functions for biochemical analyses. This technology starts a new era of biology science, where a combination of electronic and biology is first introduced. There are several types of microfluidic biochips; among them there has been a great interest in flow-based microfluidic biochips, in which the flows of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex resource units such as micropumps, switches and mixers can be built. For efficient execution, the flows of liquid routes in microfluidic biochips need to be scheduled under some resource constraints and routing constraints. The execution time of a biochemical application depends strongly on the binding and scheduling result. The most previously developed binding and scheduling algorithm is based on heuristics, and there has been no method to obtain optimal results. Considering the above, we propose an optimal method by casting the problem to a clique problem. Moreover, this paper also presents some heuristic techniques for computational time reduction. Experiments demonstrate that the proposed method is able to reduce the execution time of biochemical applications by more than 15% compared with the previous approach. Moreover, the proposed heuristic method is able to produce the results at no or little cost of optimality, in significantly shorter time than the optimal method.