Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP
Summary :
Sequence diagrams are often used in the modular design of softwares. In this paper, we propose a method to verify correctness of sequence diagrams. With this method, using the process algebra CSP, concurrent systems can be synthesized from a number of sequence diagrams. We define new CSP operators for the synthesis of sequence diagrams. We also report on a tool implementing our synthesis method and demonstrate how the tool analyzes sequence diagrams.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.2 pp.495-504
- Publication Date
- 2013/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.495
- Type of Manuscript
- Special Section PAPER (Special Section on Mathematical Systems Science and its Applications)
- Category
- Concurrent Systems
Authors
Keyword
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Tomohiro KAIZU, Yoshinao ISOBE, Masato SUZUKI, "Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 2, pp. 495-504, February 2013, doi: 10.1587/transfun.E96.A.495.
Abstract: Sequence diagrams are often used in the modular design of softwares. In this paper, we propose a method to verify correctness of sequence diagrams. With this method, using the process algebra CSP, concurrent systems can be synthesized from a number of sequence diagrams. We define new CSP operators for the synthesis of sequence diagrams. We also report on a tool implementing our synthesis method and demonstrate how the tool analyzes sequence diagrams.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.495/_p
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@ARTICLE{e96-a_2_495,
author={Tomohiro KAIZU, Yoshinao ISOBE, Masato SUZUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP},
year={2013},
volume={E96-A},
number={2},
pages={495-504},
abstract={Sequence diagrams are often used in the modular design of softwares. In this paper, we propose a method to verify correctness of sequence diagrams. With this method, using the process algebra CSP, concurrent systems can be synthesized from a number of sequence diagrams. We define new CSP operators for the synthesis of sequence diagrams. We also report on a tool implementing our synthesis method and demonstrate how the tool analyzes sequence diagrams.},
keywords={},
doi={10.1587/transfun.E96.A.495},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - Refinement and Verification of Sequence Diagrams Using the Process Algebra CSP
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 495
EP - 504
AU - Tomohiro KAIZU
AU - Yoshinao ISOBE
AU - Masato SUZUKI
PY - 2013
DO - 10.1587/transfun.E96.A.495
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2013
AB - Sequence diagrams are often used in the modular design of softwares. In this paper, we propose a method to verify correctness of sequence diagrams. With this method, using the process algebra CSP, concurrent systems can be synthesized from a number of sequence diagrams. We define new CSP operators for the synthesis of sequence diagrams. We also report on a tool implementing our synthesis method and demonstrate how the tool analyzes sequence diagrams.
ER -
English
