This paper presents analysis and design of passive RC polyphase filters (RCPFs) in tutorial style. Single-phase model of a single-stage RCPF is derived, and then, multi-stage RCPFs are analyzed and obtained some restrictions for realizable poles and zeros locations of RCPFs. Exact design methods of RCPFs with equal ripple type, and Butterworth type responses are explained for transfer function design and element value design along with some design examples.

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary analog-to-digital conversion. Also with proposed β-value estimation algorithm, there is not any digital calibration technique is required in proposed pipeline ADC. The redundancy of non-binary ADC tolerates not only the non-ideality of comparator, but also the mismatch of capacitances and the gain error of operational amplifier (op-amp) in MDAC. As a result, the power hungry high gain and wide bandwidth op-amps are not necessary for high resolution ADC, so that the reliability-enhanced pipeline ADC with simple amplifiers can operate faster and with lower power. We analyse the β-expansion of AD conversion and modify the β-encoding technique for pipeline ADC. In our knowledge, this is the first proposal architecture for non-binary pipeline ADC. The reliability of the proposed ADC architecture and β-encoding technique are verified by MATLAB simulations.

A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm².

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4–10 bit resolution and 0.4–1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.

An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 88 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 µW and 0.059 mm², respectively.

This paper presents an architecture of signal-dependent analog-to-digital converter (ADC) based on MINIMAX sampling scheme that allows achieving high data compression rate and power reduction. The proposed architecture consists of a conventional synchronous ADC, a timer and a peak detector. AD conversion is carried out only when input signal peaks are detected. To improve the accuracy of signal reconstruction, MINIMAX sampling is improved so that multiple points are captured for each peak, and its effectiveness is experimentally confirmed. In addition, power reduction, which is the primary advantage of the proposed signal-dependent ADC, is analytically discussed and then validated with circuit simulations.

Compressive sensing enables quite lower sampling rate compared with Nyquist sampling. As long as the signal is sparsity in some basis, the random sampling with CS can be employed. In order to make CS applied in the practice, the Analog to Information Converter (AIC) should be involved. Based on the Limited Random Sequence (LRS) modulation, the AIC with LRS can be designed with high performance according to the fixed sparsity. However, if the sparsity of the signal varies with time, the original AIC with LRS is not efficient. In this paper, the adaptive AIC which adapts its scheme of LRS according to the variation of the sparsity is proposed and the prototype system is designed. Due to the adaption of the AIC with the scheme of LRS, the sampling rate can be further reduced. The simulation results confirm the performance of the proposed adaptive AIC scheme. The prototype system can successfully fulfil the random sampling and adapt to the variation of sparsity, which verify and consolidate the validity and feasibility for the future implementation of adaptive AIC on chip.

A design methodology for implementation of low-noise switched-capacitor low-pass filter (SC LPF) with small capacitance spread is proposed. The proposed method is focused on the reduction of operational amplifier noise transfer gain at low frequencies and the reduction of total capacitance. A new SC LPF topology is proposed in order to adapt the correlated double sampling and charge scaling technique at the same time. Design examples show that proposed filter reduces the total capacitance by 65% or more compared to the conventional one without having significant increase in noise transfer gain.

The design and measured results of a 120 GHz/140 GHz dual-channel OOK (ON-OFF Keying) receiver are presented in this paper. Because a signal with very wide frequency width is difficult to process in a single-channel receiver, a dual-channel configuration with channel selection is adopted in the proposed receiver. The proposed receiver is fabricated using 65 nm CMOS technology. The measured data rate of 3.0 and 3.6 Gbps, minimum sensitivity of -25.6 and -27.1 dBm, communication distance of 0.30 and 0.38 m are achieved in the 120- and 140-GHz receiver, respectively. The correct channel selection is achieved in the 120-GHz receiver. These results indicate the possibility of the CMOS multiband receiver operating at over 100 GHz for low-power high-speed proximity wireless communication systems.

Sequence diagrams are often used in the modular design of softwares. In this paper, we propose a method to verify correctness of sequence diagrams. With this method, using the process algebra CSP, concurrent systems can be synthesized from a number of sequence diagrams. We define new CSP operators for the synthesis of sequence diagrams. We also report on a tool implementing our synthesis method and demonstrate how the tool analyzes sequence diagrams.

A workflow net N may be extended as another workflow net N' by adding nodes and arcs. N' is intuitively called a subclass of N under protocol inheritance if we cannot distinguish those behaviors when removing the added transitions. Protocol inheritance problem is to decide whether N' is a subclass of N under protocol inheritance. It is known that the problem is decidable but is intractable. Even if N is a subnet of N', N' is not always a subclass of N under protocol inheritance. In this paper, limiting our analysis to protocol inheritance between acyclic extended free-choice workflow nets and their subnets, we gave a necessary and sufficient condition on the problem. Based on the condition, we also constructed a polynomial time procedure for solving the problem.

In our privious paper, we proposed an algorithm that determines delay times of a timed Petri net from the structural information of a signaling pathway, but Petri net structures containing cycles and inhibitory arcs were not considered. This paper provides conditions for cycle-contained Petri nets to have reasonable delay times. Furthermore, handling of inhibitory arcs are discussed in terms of the reaction rate of inhibitory interaction in signaling pathway, especially the conversion process of Petri net with inhibitory arc to the one without inhibitory arc is given.

In this paper, we propose an optimal supervisory control method for discrete event systems (DESs) that have different preferences. In our previous work, we proposed an optimal supervisory control method based on reinforcement learning. In this paper, we extend it and consider a system that consists of several local systems. This system is modeled by a decentralized DES (DDES) that consists of local DESs, and is supervised by a central supervisor. In addition, we consider that the supervisor and each local DES have their own preferences. Each preference is represented by a preference function. We introduce the new value function based on the preference functions. Then, we propose the learning method of the optimal supervisor based on reinforcement learning for the DDESs. The supervisor learns how to assign the control pattern so as to maximize the value function for the DDES. The proposed method shows the general framework of optimal supervisory control for the DDES that consists of several local systems with different preferences. We show the efficiency of the proposed method through a computer simulation.

A Boolean network model is one of the models of gene regulatory networks, and is widely used in analysis and control. Although a Boolean network is a class of discrete-time nonlinear systems and expresses the synchronous behavior, it is important to consider the asynchronous behavior. In this paper, using a Petri net, a new modeling method of asynchronous Boolean networks with control inputs is proposed. Furthermore, the optimal control problem of Petri nets expressing asynchronous Boolean networks is formulated, and is reduced to an integer programming problem. The proposed approach will provide us one of the mathematical bases of control methods for gene regulatory networks.

A timed Petri net, an extended model of an ordinary Petri net with introduction of discrete time delay in firing activity, is practically useful in performance evaluation of real-time systems and so on. Unfortunately though, it is often too difficult to solve (efficiently) even most basic problems in timed Petri net theory. This motivates us to do research on analyzing complexity of Petri net problems and on designing efficient and/or heuristic algorithms. The minimum initial marking problem of timed Petri nets (TPMIM) is defined as follows: “Given a timed Petri net, a firing count vector X and a nonnegative integer π, find a minimum initial marking (an initial marking with the minimum total token number) among those initial ones M each of which satisfies that there is a firing scheduling which is legal on M with respect to X and whose completion time is no more than π, and, if any, find such a firing scheduling.” In a production system like factory automation, economical distribution of initial resources, from which a schedule of job-processings is executable, can be formulated as TPMIM. The subject of the paper is to propose two pseudo-polynomial time algorithms TPM and TMDLO for TPMIM, and to evaluate them by means of computer experiment. Each of the two algorithms finds an initial marking and a firing sequence by means of algorithms for MIM (the initial marking problem for non-timed Petri nets), and then converts it to a firing scheduling of a given timed Petri net. It is shown through our computer experiments that TPM has highest capability among our implemented algorithms including TPM and TMDLO.

The authors propose a method to make a movement plan for relocation of the railway cars in preparation for the final assembly. It obtains solution through three steps. The first step is to extract the order constraints between the movements of the railway cars based on their locations before and after relocation. The second step is to introduce the movement which puts a railway car into another location temporarily, in order to avoid a deadlock in the movements. And the final step is to obtain the movement order for carrying out the relocation in the shortest time in accordance with the calculated order constraints by using the genetic algorithm (GA). The order constraints are resolved in advance and therefore the movement order can easily be decided by GA. As the result, the developed system takes time shorter than an expert for planning the relocation.

Blocking artifacts are introduced in many block-based coding systems, and its reduction can significantly improve the subjective quality of compressed video. The H.264/AVC uses an in-loop deblocking filter to remove the blocking artifacts. The filter considers some coding conditions in its adaptive deblocking filtering such as coded block pattern (CBP), motion vector, macroblock type, etc. for inter-predicted blocks, however, it does not consider much for intra-coded blocks. In this paper, we utilize the human visual system (HVS) characteristic and the local characteristic of image blocks to modify the boundary strength (BS) of the intra-deblocking filter in order to gain improvement in the subjective quality and also to reduce the complexity in filtering intra coded slices. In addition, we propose a low-complexity deblocking method which utilizes the correlation between vertical and horizontal boundaries of a block in inter coded slices. Experimental results show that our proposed method achieves not only significant gain in the subjective quality but also some PSNR gain, and reduces the computational complexity of the deblocking filter by 36.23% on average.

In this paper, we propose a new method for wideband spectrum sensing using compressed measurements of the received wideband signal; we can directly separate information of the sub-channels and perform detection in each. Wideband spectrum sensing empowers us to rapidly access the vacant sub-channels in high utilization regime. Regarding the fact that at each time instant some sub-channels are vacant, the received signal is sparse in some bases. Then we could apply the Compressive Sensing (CS) algorithms and take the compressed measurements. On the other hand, the primary user signals in different sub-channels could have different modulation types; therefore, the signal in each sub-channel is chosen among a signal space. Knowing these signal spaces, the secondary user could separate information of different sub-channels employing the compressed measurements. We perform filtering and detection based on these compressed measurements; this decreases the computational complexity of the wideband spectrum sensing. In addition, we model the received wideband signal as a vector which has a block-sparse representation on a basis consisting of all sub-channel bases whose elements occur in clusters. Based on this feature of the received signal, we propose another wideband spectrum sensing method with lower computational complexity. In order to evaluate the performance of the proposed method, we employ the Monte-Carlo simulation. According to simulations if the compression rate is selected appropriately according to the CS theorems and the problem model, the detection performance of our method leads to the performance of the ideal filter bank-based method, which uses the ideal and impractical narrow band filters.

This paper presents an efficient approach for logarithmic and anti-logarithmic converters which can be used in the arithmetic unit of hybrid number system processors and logarithm/exponent function generators in DSP applications. By employing the novel quasi-symmetrical difference method with only the simple shift-add logic and the look-up table, the proposed approach can reduce the hardware area and improve the conversion speed significantly while achieve similar accuracy compared with the previous methods. The implementation results in both FPGA and 0.18-µm CMOS technology are also presented and discussed.

We study the role of energy conversion in phase regulation of frequency entrainment. For an open dynamical system that interacts with its environment, energy conversion in the system is the key to a wide variety of nonlinear phenomena including frequency entrainment. In this paper, using the standard notion of energy, we study the phenomena of frequency entrainment by periodic forces in two different types of oscillations: libration and rotation. Theoretical analysis shows a relationship between phase regulation and energy conversion in the entrainment phenomena. Both of them are explained as a common phase regulation. On the other hand, no common relationship between transient behaviors and energy conversion is identified for the two different types of oscillations. For libration, the development of frequency entrainment does not depend on the energy conversion. The energy input to the oscillator affects the amplitude of libration. For the rotation, the development of frequency entrainment is governed by the amount of energy conversion. The energy input to the system directly regulates the phase of rotation, in other words, controls the entrainment phenomenon. These results suggest a different dynamical and control origin behind the two types of entrainment phenomena as the energy conversion in the systems.

Multihigh-dimensional chaotic systems were reduced to low-dimensional space embedded equations (SEEs), and their macroscopic and statistical properties were investigated using eigen analysis of the moment vector equation (MVE) of the SEE. First, the state space of the target system was discretized into a finite discrete space. Next, an embedding from the discrete space to a low-dimensional discrete space was defined. The SEE of the target system was derived using the embedding. Finally, eigen analysis was applied to the MVE of the SEE to derive the properties of the target system. The geometric increase in the dimension of the MVE with the dimension of the target system was avoided by using the SEE. The pdfs of arbitrary elements in the target nonlinear system were derived without a reduction in accuracy due to dimension reduction. Moreover, since the dynamics of the system were expressed by the eigenvalues of the MVE, it was possible to identify multiple steady states that cannot be done using numerical simulation. This approach can thus be used to analyze the macroscopic and statistical properties of multi-dimensional chaotic systems.

Reed-Solomon (RS) code is one of the well-known and widely used error correction codes. Among the components of a hardware RS decoder, the key equation solver (KES) unit occupies a relatively large portion of the hardware. It is important to develop an efficient KES architecture to implement efficient RS decoders. In this paper, a novel polynomial division technique used in the Euclidean algorithm (EA) of the KES is presented which achieves the short critical path delay of one Galois multiplier and one Galois adder. Then a KES architecture with the EA is proposed which is efficient in the sense of the product of area and time.

This paper presents a power analysis that applies to elliptic curves over generalized Mersenne prime field F_p. This prime field enables efficient modular reductions which influence the computational performance of an elliptic curve cryptosystem. The general modular reductions stochastically calculate extra operations. Some studies showed the possibility of power analysis attacks to scalar multiplication with a unified code by using the statistical information of extra operations. In this paper, we present the statistical experiment and possibility of attacks, and propose the more sensitive attack and the countermeasure without performance impact.

In the construction of a no-linear key-stream generator, self-shrinking is an established way of getting the binary pseudo-random periodic sequences in cryptography design. In this paper, using the theoretical analysis, we mainly study the self-shrinking sequence based on the l-sequence, and the theoretical results reflect its good cryptography properties accurately, such that it has the last period T = p^e(p-1)/2 when T is an odd number, and the expected value of its autocorrelation belongs to {0,1/T and the variance is O(T/ln⁴T). Furthermore, we find that the 2-adic complexity of the self-shrinking sequence based on the l-sequence is large enough to resist the Rational Approximation attack.

In this paper, we present a construction of (n,k,d,m) secure regenerating codes for distributed storage systems against eavesdroppers that can observe either data stored in at most m storage nodes or downloaded data for repairing at most m failed nodes in a network where m < k ≤ d ≤ n-1. The (n,k,d,m) secure regenerating code is based on an (n,k,d) minimum bandwidth regenerating (MBR) code, which was proposed by Rashmi, Shah and Kumar as optimal exact-regenerating codes, for all values of the parameters (n,k,d). The (n,k,d,m) secure regenerating codes have the security as a secret sharing scheme such that even if an eavesdropper knows either data stored in at most m storage nodes or downloaded data for repairing at most m failed nodes, no information about data leaks to the eavesdropper.

Many people have faced mortal risks due to sudden disasters such as earthquakes, fires, and terrorisms, etc. In disasters where most people become panic, it is important to grasp disaster positions immediately and to find out some appropriate evacuation routes. We previously proposed the specific evacuation support system named as Emergency Rescue Evacuation Support System (ERESS). ERESS is based on Mobile Ad-hoc network (MANET) and aims to reduce the number of victims in panic-type disasters. This system consists of mobile terminals with advanced disaster recognition algorithm and various sensors such as acceleration, angular velocity and earth magnetism. However, the former ERESS did not have the clear criteria to detect the disaster outbreak. In this paper, we propose a new disaster recognition algorithm by Support Vector Machine (SVM) which is a kind of machine learning. In this method, an ERESS mobile terminal learns the behaviors of its holder by SVM. The SVM acquires the decision boundary based on the sensing data of the terminal holder, and it is judged whether to be the emergency. We show the validity of the proposed method by panic-type experiments.

Experiments usually aim to study how changes in various factors affect the response variable of interest. Since the response model used most often at present in experimental design is expressed through the effect of each factor, it is straightforward to ascertain how each factor affects the response variable. However, since the response model contains redundant parameters, in the analysis of variance we must calculate the degrees of freedom defined by the number of independent parameters. In this letter, we propose the idea of calculating the degrees of freedom over the model based on an orthonormal system for the first time. In this way, we can easily obtain the number of independent parameters associated with any component, which reduces the risk of mistakes in the calculation of the number of independent parameters and facilitates the implementation of estimation procedures.

In this paper, we give some results towards the conjecture that σ_2^t+1l-1,2^t are the only nonlinear balanced elementary symmetric Boolean functions where t and l are positive integers. At first, a unified and simple proof of some earlier results is shown. Then a property of balanced elementary symmetric Boolean functions is presented. With this property, we prove that the conjecture is true for n=2^m+2^t-1 where m,t (m>t) are two non-negative integers, which verified the conjecture for a large infinite class of integer n.