An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter

Toshihiro KONISHI; Keisuke OKUNO; Shintaro IZUMI; Masahiko YOSHIMOTO; Hiroshi KAWAGUCHI

doi:10.1587/transfun.E96.A.434

An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter

Toshihiro KONISHI, Keisuke OKUNO, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

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This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm².

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.2 pp.434-442

Publication Date: 2013/02/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.434

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Toshihiro KONISHI, Keisuke OKUNO, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, "An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 2, pp. 434-442, February 2013, doi: 10.1587/transfun.E96.A.434.
Abstract: This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm².
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.434/_p

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@ARTICLE{e96-a_2_434,
author={Toshihiro KONISHI, Keisuke OKUNO, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter},
year={2013},
volume={E96-A},
number={2},
pages={434-442},
abstract={This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm².},
keywords={},
doi={10.1587/transfun.E96.A.434},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 434
EP - 442
AU - Toshihiro KONISHI
AU - Keisuke OKUNO
AU - Shintaro IZUMI
AU - Masahiko YOSHIMOTO
AU - Hiroshi KAWAGUCHI
PY - 2013
DO - 10.1587/transfun.E96.A.434
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2013
AB - This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm².
ER -