The fingerprint verification system is widely used in mobile devices because of fingerprint's distinctive features and ease of capture. Typically, mobile devices utilize small sensors, which have limited area, to capture fingerprint. Meanwhile, conventional fingerprint feature extraction methods need detailed fingerprint information, which is unsuitable for those small sensors. This paper proposes a novel fingerprint verification method for small area sensors based on deep learning. A systematic method combines deep convolutional neural network (DCNN) in a Siamese network for feature extraction and XGBoost for fingerprint similarity training. In addition, a padding technique also introduced to avoid wraparound error problem. Experimental results show that the method achieves an improved accuracy of 66.6% and 22.6% in the FingerPassDB7 and FVC2006DB1B dataset, respectively, compared to the existing methods.

Many applications, such as image signal processing, has an inherent tolerance for insignificant inaccuracies. Multiplication is a key arithmetic function for many applications. Approximate multipliers are considered an efficient technique to trade off energy relative to performance and accuracy for the error-tolerant applications. Here, we design and analyze four approximate multipliers that demonstrate lower power consumption and shorter critical path delay than the conventional multiplier. They employ an approximate tree compressor that halves the height of the partial product tree and generates a vector to compensate accuracy. Compared with the conventional Wallace tree multiplier, one of the evaluated 8-bit approximate multipliers reduces power consumption and critical path delay by 36.9% and 38.9%, respectively. With a 0.25% normalized mean error distance, the silicon area required to implement the multiplier is reduced by 50.3%. Our multipliers outperform the previously proposed approximate multipliers relative to power consumption, critical path delay, and design area. Results from two image processing applications also demonstrate that the qualities of the images processed by our multipliers are sufficiently accurate for such error-tolerant applications.

This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm2.

A new clock gating circuit suitable for shift register is presented. The proposed clock gating circuit that consists of basic NOR gates is low power and small area. The power consumption of a 16-bit shift register implemented with the proposed clock gating circuit is about 66% lower than that found when using the conventional design.

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core circuits for high-performance displays based on low-noise on-chip references and dual-mode inputs with the requirements of limited pins, low power, and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipeline architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip current and voltage references to improve noise performance with a power-off function for portable applications. The prototype ADC is implemented in a 0.18 µm CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The prototype ADC shows the measured DNL and INL within 0.49LSB and 0.69LSB, and the SNDR and SFDR exceeding 38 dB and 50 dB for inputs up to the Nyquist frequency at 240 MS/s. The ADC consumes 104 mW at 240 MS/s and an active die area is 1.36 mm2 .

The cable length in wired serial data communication is limited because the limited bandwidth of a long cable introduces ISI (Inter Symbol Interference). A line equalizer can be used at the receiver to extend the channel bandwidth. This paper proposes a low-power and small-area analog adaptive line equalizer for 100-Mb/s operation on UTP (Unshielded Twisted Pair) cable up to 100 m. The proposed adaptive line equalizer is fabricated with 0.35-µm CMOS process, consumes 19 mW and occupies only 0.07 mm2 Measurement results show that the prototype can operate at data rate of 100 Mb/s on a 100-m cable and 155 Mb/s on a 50-m cable.