This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm2.

This paper presents optimum and sub-optimal designs of noise-shaping FIR filters for single- and multi-bit data converters. In the designs, only three parameters, the number of taps, oversampling ratio (OSR) and l1-norm of the filter coefficients are specified, and the in-band peak of the amplitude response is minimized under the specifications. The minimization problem is formulated with the overload-free condition, which guarantees the rigorous stability, and an overload-free converter generates no distortion in any output signals. In the optimum design, the minimization problem is directly and exactly solved, but the sub-optimal method solves this problem by iteratively utilizing the simplex method. The iterative sub-optimal method without the exact optimality is far faster and more efficient than the optimum method. In design examples, optimum and sub-optimal noise-shaping FIR filters for single- and multi-bit data converters are designed, and their optimal performance is revealed. For single-bit data converters with OSR 64, a noise-shaping FIR filter is designed and then shown to achieve a signal to noise and distortion ratio (SNDR) 107.6 [dB] in the band of interest.

This paper presents a technique for improving the SNR and resolution of complex bandpass ΔΣADCs which are used for wireless communication systems such as cellular phone, wireless LAN and Bluetooth. Oversampling and noise-shaping are used to achieve high accuracy of a ΔΣAD modulator. However when a multi-bit internal DAC is used inside a modulator, nonlinearities of the DAC are not noise-shaped and the SNR of the ΔΣADC degrades. For the conversion of complex intermediate frequency (IF) input signals, a complex bandpass ΔΣAD modulator can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. This paper proposes a new noise-shaping algorithm--implemented by adding simple digital circuitry--to reduce the effects of nonlinearities in multi-bit DACs of complex bandpass ΔΣAD modulators. We have performed simulation with MATLAB to verify the effectiveness of the algorithm, and the results show that the proposed algorithm can improve the SNR of a complex bandpass ΔΣADC with nonlinear internal multi-bit DACs.

This paper presents data coding techniques for a stable single-bit noise-shaping quantizer, which has a cascade structure of a multi-bit ΣΔ modulator and a binary interpolator. The binary interpolator chooses a pre-optimized binary vector for each input sample and successively generates the chosen binary vector as an output bit stream. The binary vectors can have different lengths. The paper also proposes two methods to evaluate and bound output errors of a binary interpolator. A multi-bit ΣΔ modulator is designed to cause no overload for all possible input signals whose amplitudes are bounded to a specified level, and thus the ΣΔ modulator rigorously guarantees the stability condition. In design examples, we have evaluated Signal-to-Noise and Distortion Ratios (SNDRs) and noise spectra and then confirmed that our stable quantizers can sharply shape output noise spectra.

This paper proposes two novel Multi-bit Delta-Sigma Modulator (Δ Σ M) architectures based on a Dual-Quantization architecture. By using multi-bit quantization with single-bit feedback, Both eliminate the need for a multi-bit digital-to-analog converter (DAC) in the feedback loop. The first is a Digital quantization-Error Canceling Multi-bit (DECM)-Δ Σ M architecture that is able to achieve high resolution at a low oversampling ratio (OSR) because, by adjusting the coefficients of both analog and digital circuits, it is able to cancel completely the quantization error injected into the single-bit quantizer. Simulation results show that a signal-to-quantization-noise ratio of 90 dB is obtained with 3rd order 5-bit quantization DECM-Δ Σ M at an OSR of 32. The second architecture, an analog-to-digital mixed (ADM)-Δ Σ M architecture, uses digital integrators in place of the analog integrator circuits used in the Δ Σ M. This architecture reduces both die area and power dissipation. We estimate that a (2+2)-th order ADM-Δ Σ M with two analog-integrators and two digital-integrators will reduce the area of a 4-th order Δ Σ M by 15%.

We describe low supply voltage analog circuit techniques for voice- and audio-band interfaces. These techniques can lower the supply voltage to 1 V, which is the voltage of a one-NiCd-cell battery. We have applied them in a swingsuppression noise-shaping method, and using this method, have fabricated A/D and D/A converters for the voice and audio bands. These converters operate with a 1 V power supply and have 13-bit and 17-bit accuracy in the audio-band and power consumption of about 1 mW. This performance proves that our techniques are sufficient for baseband analog interfaces.

This paper describes an oversampling analog-to-digital converter (ADC) suitable for PCM codes. Non-linear 5-level quantizer is implemented to noise-shaping modulator. This ADC meets the specifications of ITU-T G.712, in spite of using first order delta-sigma modulator, and realizes low power operation. This chip is fabricated in 0.8 µm double-poly and double-metal CMOS process and occupies a chip area of 15 mm2. Maximum power consumption is 12.8 mW with a single +3 V power supply including DAC and TONE generator.

A multi-stage noise-shaping (MASH) A/D converter combining an RC-integrator and a digital correction technique for high accuracy is described. Using 1.2-µm BiCMOS technology, we developed an A/D converter for digital audio with an S/N ratio of over 100 dB. This paper discusses the principles of MASH technology with an RC-integrator, the technique for correcting RC variation, and the experimental results obtained with a fabricated chip.