IEICE TRANSACTIONS on Fundamentals
Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers
Summary :
Post-Silicon Tunable (PST) buffers are widely adopted in high-performance integrated circuits to fix timing violations introduced by process variations. In typical optimization procedures, the statistical timing analysis of the circuits with PST clock buffers will be executed more than 2000 times for large scale circuits. Therefore, the efficiency of the statistical timing analysis is crucial to the PST clock buffer optimization algorithms. In this paper, we propose a stochastic collocation based efficient statistical timing analysis method for circuits with PST buffers. In the proposed method, we employ the Howard algorithm to calculate the clock periods of the circuits on less than 100 deterministic sparse-grid collocation points. Afterwards, we use these obtained clock periods to derive the yield of the circuits according to the stochastic collocation theory. Compared with the state-of-the-art statistical timing analysis method for the circuits with PST clock buffers, the proposed method achieves up to 22X speedup with comparable accuracy.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.11 pp.2227-2235
- Publication Date
- 2014/11/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.2227
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Xingbao ZHOU
Fudan University
Fan YANG
Fudan University
Hai ZHOU
Northwestern University
Min GONG
IBM China Research Lab
Hengliang ZHU
Fudan University
Ye ZHANG
Fudan University
Xuan ZENG
Fudan University
Keyword
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Xingbao ZHOU, Fan YANG, Hai ZHOU, Min GONG, Hengliang ZHU, Ye ZHANG, Xuan ZENG, "Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 11, pp. 2227-2235, November 2014, doi: 10.1587/transfun.E97.A.2227.
Abstract: Post-Silicon Tunable (PST) buffers are widely adopted in high-performance integrated circuits to fix timing violations introduced by process variations. In typical optimization procedures, the statistical timing analysis of the circuits with PST clock buffers will be executed more than 2000 times for large scale circuits. Therefore, the efficiency of the statistical timing analysis is crucial to the PST clock buffer optimization algorithms. In this paper, we propose a stochastic collocation based efficient statistical timing analysis method for circuits with PST buffers. In the proposed method, we employ the Howard algorithm to calculate the clock periods of the circuits on less than 100 deterministic sparse-grid collocation points. Afterwards, we use these obtained clock periods to derive the yield of the circuits according to the stochastic collocation theory. Compared with the state-of-the-art statistical timing analysis method for the circuits with PST clock buffers, the proposed method achieves up to 22X speedup with comparable accuracy.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.2227/_p
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@ARTICLE{e97-a_11_2227,
author={Xingbao ZHOU, Fan YANG, Hai ZHOU, Min GONG, Hengliang ZHU, Ye ZHANG, Xuan ZENG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers},
year={2014},
volume={E97-A},
number={11},
pages={2227-2235},
abstract={Post-Silicon Tunable (PST) buffers are widely adopted in high-performance integrated circuits to fix timing violations introduced by process variations. In typical optimization procedures, the statistical timing analysis of the circuits with PST clock buffers will be executed more than 2000 times for large scale circuits. Therefore, the efficiency of the statistical timing analysis is crucial to the PST clock buffer optimization algorithms. In this paper, we propose a stochastic collocation based efficient statistical timing analysis method for circuits with PST buffers. In the proposed method, we employ the Howard algorithm to calculate the clock periods of the circuits on less than 100 deterministic sparse-grid collocation points. Afterwards, we use these obtained clock periods to derive the yield of the circuits according to the stochastic collocation theory. Compared with the state-of-the-art statistical timing analysis method for the circuits with PST clock buffers, the proposed method achieves up to 22X speedup with comparable accuracy.},
keywords={},
doi={10.1587/transfun.E97.A.2227},
ISSN={1745-1337},
month={November},}
Copy
TY - JOUR
TI - Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2227
EP - 2235
AU - Xingbao ZHOU
AU - Fan YANG
AU - Hai ZHOU
AU - Min GONG
AU - Hengliang ZHU
AU - Ye ZHANG
AU - Xuan ZENG
PY - 2014
DO - 10.1587/transfun.E97.A.2227
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2014
AB - Post-Silicon Tunable (PST) buffers are widely adopted in high-performance integrated circuits to fix timing violations introduced by process variations. In typical optimization procedures, the statistical timing analysis of the circuits with PST clock buffers will be executed more than 2000 times for large scale circuits. Therefore, the efficiency of the statistical timing analysis is crucial to the PST clock buffer optimization algorithms. In this paper, we propose a stochastic collocation based efficient statistical timing analysis method for circuits with PST buffers. In the proposed method, we employ the Howard algorithm to calculate the clock periods of the circuits on less than 100 deterministic sparse-grid collocation points. Afterwards, we use these obtained clock periods to derive the yield of the circuits according to the stochastic collocation theory. Compared with the state-of-the-art statistical timing analysis method for the circuits with PST clock buffers, the proposed method achieves up to 22X speedup with comparable accuracy.
ER -
English
