For variation-aware capacitance extraction, stochastic collocation method (SCM) based on Homogeneous Chaos expansion has the exponential convergence rate for Gaussian geometric variations, and is considered as the optimal solution using a quadratic model to model the parasitic capacitances. However, when geometric variations are measured from the real test chip, they are not necessarily Gaussian, which will significantly compromise the exponential convergence property of SCM. In order to pursue the exponential convergence, in this paper, a generalized stochastic collocation method (gSCM) based on generalized Polynomial Chaos (gPC) expansion and generalized Sparse Grid quadrature is proposed for variation-aware capacitance extraction that further considers the arbitrary random probability of real geometric variations. Additionally, a recycling technique based on Minimum Spanning Tree (MST) structure is proposed to reduce the computation cost at each collocation point, for not only "recycling" the initial value, but also "recycling" the preconditioning matrix. The exponential convergence of the proposed gSCM is clearly shown in the numerical results for the geometric variations with arbitrary random probability.

In this paper, we propose an Adaptive Stochastic Collocation Method for block-based Statistical Static Timing Analysis (SSTA). A novel adaptive method is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on Homogeneous Chaos expansion. In order to approximate the key atomic operator MAX in the full random space during timing analysis, the proposed method adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions. Compared with the existing stochastic collocation methods, including the one using dimension reduction technique and the one using Sparse Grid technique, the proposed method has 10x improvements in the accuracy while using the same order of computation time. The proposed algorithm also shows great improvement in accuracy compared with a moment matching method. Compared with the 10,000 Monte Carlo simulations on ISCAS85 benchmark circuits, the results of the proposed method show less than 1% error in the mean and variance, and nearly 100x speeds up.

In this paper, we propose a Modified nested sparse grid based Adaptive Stochastic Collocation Method (MASCM) for block-based Statistical Static Timing Analysis (SSTA). The proposed MASCM employs an improved adaptive strategy derived from the existing Adaptive Stochastic Collocation Method (ASCM) to approximate the key operator MAX during timing analysis. In contrast to ASCM which uses non-nested sparse grid and tensor product quadratures to approximate the MAX operator for weakly and strongly nonlinear conditions respectively, MASCM proposes a modified nested sparse grid quadrature to approximate the MAX operator for both weakly and strongly nonlinear conditions. In the modified nested sparse grid quadrature, we firstly construct the second order quadrature points based on extended Gauss-Hermite quadrature and nested sparse grid technique, and then discard those quadrature points that do not contribute significantly to the computation accuracy to enhance the efficiency of the MAX approximation. Compared with the non-nested sparse grid quadrature, the proposed modified nested sparse grid quadrature not only employs much fewer collocation points, but also offers much higher accuracy. Compared with the tensor product quadrature, the modified nested sparse grid quadrature greatly reduced the computational cost, while still maintains sufficient accuracy for the MAX operator approximation. As a result, the proposed MASCM provides comparable accuracy while remarkably reduces the computational cost compared with ASCM. The numerical results show that with comparable accuracy MASCM has 50% reduction in run time compared with ASCM.

Post-Silicon Tunable (PST) buffers are widely adopted in high-performance integrated circuits to fix timing violations introduced by process variations. In typical optimization procedures, the statistical timing analysis of the circuits with PST clock buffers will be executed more than 2000 times for large scale circuits. Therefore, the efficiency of the statistical timing analysis is crucial to the PST clock buffer optimization algorithms. In this paper, we propose a stochastic collocation based efficient statistical timing analysis method for circuits with PST buffers. In the proposed method, we employ the Howard algorithm to calculate the clock periods of the circuits on less than 100 deterministic sparse-grid collocation points. Afterwards, we use these obtained clock periods to derive the yield of the circuits according to the stochastic collocation theory. Compared with the state-of-the-art statistical timing analysis method for the circuits with PST clock buffers, the proposed method achieves up to 22X speedup with comparable accuracy.