IEICE TRANSACTIONS on Fundamentals
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement
Summary :
Due to the progress of the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay variations. To recover the timing violations, delay tuning methods insert programmable delay elements called PDEs into the clock tree before fabrication and tune their delays after fabrication. The yield improvement of existing methods is not enough. In this paper, a delay tuning method of PDEs with an ordered finite set of delays is proposed for the yield improvement. The proposed delay tuning method is based on the modified Bellman-Ford algorithm. Therefore, its optimality is guaranteed and its time complexity is polynomial. In the experiments under Monte-Carlo simulation, the yield of the proposed method is improved higher when the number of delays in each PDE is increased.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.12 pp.2443-2450
- Publication Date
- 2014/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.2443
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
Authors
Hayato MASHIKO
University of Aizu
Yukihide KOHIRA
University of Aizu
Keyword
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Hayato MASHIKO, Yukihide KOHIRA, "A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 12, pp. 2443-2450, December 2014, doi: 10.1587/transfun.E97.A.2443.
Abstract: Due to the progress of the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay variations. To recover the timing violations, delay tuning methods insert programmable delay elements called PDEs into the clock tree before fabrication and tune their delays after fabrication. The yield improvement of existing methods is not enough. In this paper, a delay tuning method of PDEs with an ordered finite set of delays is proposed for the yield improvement. The proposed delay tuning method is based on the modified Bellman-Ford algorithm. Therefore, its optimality is guaranteed and its time complexity is polynomial. In the experiments under Monte-Carlo simulation, the yield of the proposed method is improved higher when the number of delays in each PDE is increased.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.2443/_p
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@ARTICLE{e97-a_12_2443,
author={Hayato MASHIKO, Yukihide KOHIRA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement},
year={2014},
volume={E97-A},
number={12},
pages={2443-2450},
abstract={Due to the progress of the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay variations. To recover the timing violations, delay tuning methods insert programmable delay elements called PDEs into the clock tree before fabrication and tune their delays after fabrication. The yield improvement of existing methods is not enough. In this paper, a delay tuning method of PDEs with an ordered finite set of delays is proposed for the yield improvement. The proposed delay tuning method is based on the modified Bellman-Ford algorithm. Therefore, its optimality is guaranteed and its time complexity is polynomial. In the experiments under Monte-Carlo simulation, the yield of the proposed method is improved higher when the number of delays in each PDE is increased.},
keywords={},
doi={10.1587/transfun.E97.A.2443},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2443
EP - 2450
AU - Hayato MASHIKO
AU - Yukihide KOHIRA
PY - 2014
DO - 10.1587/transfun.E97.A.2443
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2014
AB - Due to the progress of the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay variations. To recover the timing violations, delay tuning methods insert programmable delay elements called PDEs into the clock tree before fabrication and tune their delays after fabrication. The yield improvement of existing methods is not enough. In this paper, a delay tuning method of PDEs with an ordered finite set of delays is proposed for the yield improvement. The proposed delay tuning method is based on the modified Bellman-Ford algorithm. Therefore, its optimality is guaranteed and its time complexity is polynomial. In the experiments under Monte-Carlo simulation, the yield of the proposed method is improved higher when the number of delays in each PDE is increased.
ER -
English
