Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization
Summary :
Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1455-1466
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1455
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Jun SHIOMI
Kyoto University
Tohru ISHIHARA
Kyoto University
Hidetoshi ONODERA
Kyoto University
Keyword
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Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, "Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 7, pp. 1455-1466, July 2015, doi: 10.1587/transfun.E98.A.1455.
Abstract: Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1455/_p
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@ARTICLE{e98-a_7_1455,
author={Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization},
year={2015},
volume={E98-A},
number={7},
pages={1455-1466},
abstract={Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.},
keywords={},
doi={10.1587/transfun.E98.A.1455},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1455
EP - 1466
AU - Jun SHIOMI
AU - Tohru ISHIHARA
AU - Hidetoshi ONODERA
PY - 2015
DO - 10.1587/transfun.E98.A.1455
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.
ER -
English
