IEICE TRANSACTIONS on Fundamentals
TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance
Summary :
The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.8 pp.1796-1805
- Publication Date
- 2015/08/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1796
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Ya-Shih HUANG
National Chiao Tung University
Han-Yuan CHANG
National Chiao Tung University
Juinn-Dar HUANG
National Chiao Tung University
Keyword
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Ya-Shih HUANG, Han-Yuan CHANG, Juinn-Dar HUANG, "TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 8, pp. 1796-1805, August 2015, doi: 10.1587/transfun.E98.A.1796.
Abstract: The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1796/_p
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@ARTICLE{e98-a_8_1796,
author={Ya-Shih HUANG, Han-Yuan CHANG, Juinn-Dar HUANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance},
year={2015},
volume={E98-A},
number={8},
pages={1796-1805},
abstract={The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.},
keywords={},
doi={10.1587/transfun.E98.A.1796},
ISSN={1745-1337},
month={August},}
Copy
TY - JOUR
TI - TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1796
EP - 1805
AU - Ya-Shih HUANG
AU - Han-Yuan CHANG
AU - Juinn-Dar HUANG
PY - 2015
DO - 10.1587/transfun.E98.A.1796
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2015
AB - The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.
ER -
English
