IEICE TRANSACTIONS on Fundamentals
Foreground Segmentation Using Morphological Operator and Histogram Analysis for Indoor Applications
Summary :
This paper proposes a foreground segmentation method for indoor environments using depth images only. It uses a morphological operator and histogram analysis to segment the foreground. In order to compare the accuracy for foreground segmentation, we use metric measurements of false positive rate (FPR), false negative rate (FNR), total error (TE), and a similarity measure (S). A series of experimental results using video sequences collected under various circumstances are discussed. The proposed system is also designed in a field-programmable gate array (FPGA) implementation with low hardware resources.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.9 pp.1998-2003
- Publication Date
- 2015/09/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1998
- Type of Manuscript
- LETTER
- Category
- Vision
Authors
Kyounghoon JANG
Dong-A University
Geun-Jun KIM
Dong-A University
Hosang CHO
Dong-A University
Bongsoon KANG
Dong-A University
Keyword
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Kyounghoon JANG, Geun-Jun KIM, Hosang CHO, Bongsoon KANG, "Foreground Segmentation Using Morphological Operator and Histogram Analysis for Indoor Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 9, pp. 1998-2003, September 2015, doi: 10.1587/transfun.E98.A.1998.
Abstract: This paper proposes a foreground segmentation method for indoor environments using depth images only. It uses a morphological operator and histogram analysis to segment the foreground. In order to compare the accuracy for foreground segmentation, we use metric measurements of false positive rate (FPR), false negative rate (FNR), total error (TE), and a similarity measure (S). A series of experimental results using video sequences collected under various circumstances are discussed. The proposed system is also designed in a field-programmable gate array (FPGA) implementation with low hardware resources.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1998/_p
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@ARTICLE{e98-a_9_1998,
author={Kyounghoon JANG, Geun-Jun KIM, Hosang CHO, Bongsoon KANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Foreground Segmentation Using Morphological Operator and Histogram Analysis for Indoor Applications},
year={2015},
volume={E98-A},
number={9},
pages={1998-2003},
abstract={This paper proposes a foreground segmentation method for indoor environments using depth images only. It uses a morphological operator and histogram analysis to segment the foreground. In order to compare the accuracy for foreground segmentation, we use metric measurements of false positive rate (FPR), false negative rate (FNR), total error (TE), and a similarity measure (S). A series of experimental results using video sequences collected under various circumstances are discussed. The proposed system is also designed in a field-programmable gate array (FPGA) implementation with low hardware resources.},
keywords={},
doi={10.1587/transfun.E98.A.1998},
ISSN={1745-1337},
month={September},}
Copy
TY - JOUR
TI - Foreground Segmentation Using Morphological Operator and Histogram Analysis for Indoor Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1998
EP - 2003
AU - Kyounghoon JANG
AU - Geun-Jun KIM
AU - Hosang CHO
AU - Bongsoon KANG
PY - 2015
DO - 10.1587/transfun.E98.A.1998
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2015
AB - This paper proposes a foreground segmentation method for indoor environments using depth images only. It uses a morphological operator and histogram analysis to segment the foreground. In order to compare the accuracy for foreground segmentation, we use metric measurements of false positive rate (FPR), false negative rate (FNR), total error (TE), and a similarity measure (S). A series of experimental results using video sequences collected under various circumstances are discussed. The proposed system is also designed in a field-programmable gate array (FPGA) implementation with low hardware resources.
ER -
English
