ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

Masashi TAWADA; Shinji KIMURA; Masao YANAGISAWA; Nozomu TOGAWA

doi:10.1587/transfun.E98.A.2494

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

Masashi TAWADA, Shinji KIMURA, Masao YANAGISAWA, Nozomu TOGAWA

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Non-volatile memory has many advantages such as high density and low leakage power but it consumes larger writing energy than SRAM. It is quite necessary to reduce writing energy in non-volatile memory design. In this paper, we propose write-reduction codes based on error correcting codes and reduce writing energy in non-volatile memory by decreasing the number of writing bits. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. In our write-reduction codes, every data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to the data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. Experimental results demonstrate that we have achieved writing-bits reduction by an average of 51% and energy reduction by an average of 33% compared to non-encoded memory.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.12 pp.2494-2504

Publication Date: 2015/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E98.A.2494

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: High-Level Synthesis and System-Level Design

Authors

Masashi TAWADA
  Waseda University
Shinji KIMURA
  Waseda University
Masao YANAGISAWA
  Waseda University
Nozomu TOGAWA
  Waseda University

Keyword

non-volatile memory, bit-write reduction, energy reduction, write-reduction code, error-correcting code

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Masashi TAWADA, Shinji KIMURA, Masao YANAGISAWA, Nozomu TOGAWA, "ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory" in IEICE TRANSACTIONS on Fundamentals, vol. E98-A, no. 12, pp. 2494-2504, December 2015, doi: 10.1587/transfun.E98.A.2494.
Abstract: Non-volatile memory has many advantages such as high density and low leakage power but it consumes larger writing energy than SRAM. It is quite necessary to reduce writing energy in non-volatile memory design. In this paper, we propose write-reduction codes based on error correcting codes and reduce writing energy in non-volatile memory by decreasing the number of writing bits. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. In our write-reduction codes, every data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to the data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. Experimental results demonstrate that we have achieved writing-bits reduction by an average of 51% and energy reduction by an average of 33% compared to non-encoded memory.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.2494/_p

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@ARTICLE{e98-a_12_2494,
author={Masashi TAWADA, Shinji KIMURA, Masao YANAGISAWA, Nozomu TOGAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory},
year={2015},
volume={E98-A},
number={12},
pages={2494-2504},
abstract={Non-volatile memory has many advantages such as high density and low leakage power but it consumes larger writing energy than SRAM. It is quite necessary to reduce writing energy in non-volatile memory design. In this paper, we propose write-reduction codes based on error correcting codes and reduce writing energy in non-volatile memory by decreasing the number of writing bits. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. In our write-reduction codes, every data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to the data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. Experimental results demonstrate that we have achieved writing-bits reduction by an average of 51% and energy reduction by an average of 33% compared to non-encoded memory.},
keywords={},
doi={10.1587/transfun.E98.A.2494},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2494
EP - 2504
AU - Masashi TAWADA
AU - Shinji KIMURA
AU - Masao YANAGISAWA
AU - Nozomu TOGAWA
PY - 2015
DO - 10.1587/transfun.E98.A.2494
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2015
AB - Non-volatile memory has many advantages such as high density and low leakage power but it consumes larger writing energy than SRAM. It is quite necessary to reduce writing energy in non-volatile memory design. In this paper, we propose write-reduction codes based on error correcting codes and reduce writing energy in non-volatile memory by decreasing the number of writing bits. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. In our write-reduction codes, every data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to the data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. Experimental results demonstrate that we have achieved writing-bits reduction by an average of 51% and energy reduction by an average of 33% compared to non-encoded memory.
ER -