IEICE TRANSACTIONS on Fundamentals
Signal Propagation Delay Model in Vertically Stacked Chips
Summary :
To design high quality three-dimensional integrated circuits (3-D ICs), the effect of process and design parameters on delay must be adequately understood. This paper presents an electrical circuit model of an entire structure in through silicon via (TSV) based 3-D ICs with a new equation for on-chip interconnect capacitance and then proposes an effective model for evaluating signal propagation delay in vertically stacked chips. All electrical parameter values can be calculated by the closed-form equations without a field solver. The delay model is constructed with the first- or second-order function of each parameter to the delay obtained from a typical structure. The results obtained by on-chip interconnect capacitance equations and delay model are in excellent agreement with those by a field solver and circuit simulator, respectively. We also show that the model is very useful for evaluating effects of the process and design parameters on vertical signal propagation delay such as the sensitivity and variability analysis.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.12 pp.2614-2624
- Publication Date
- 2015/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.2614
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Nanako NIIOKA
Hirosaki University
Masayuki WATANABE
Hirosaki University
Masa-aki FUKASE
Hirosaki University
Masashi IMAI
Hirosaki University
Atsushi KUROKAWA
Hirosaki University
Keyword
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Nanako NIIOKA, Masayuki WATANABE, Masa-aki FUKASE, Masashi IMAI, Atsushi KUROKAWA, "Signal Propagation Delay Model in Vertically Stacked Chips" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 12, pp. 2614-2624, December 2015, doi: 10.1587/transfun.E98.A.2614.
Abstract: To design high quality three-dimensional integrated circuits (3-D ICs), the effect of process and design parameters on delay must be adequately understood. This paper presents an electrical circuit model of an entire structure in through silicon via (TSV) based 3-D ICs with a new equation for on-chip interconnect capacitance and then proposes an effective model for evaluating signal propagation delay in vertically stacked chips. All electrical parameter values can be calculated by the closed-form equations without a field solver. The delay model is constructed with the first- or second-order function of each parameter to the delay obtained from a typical structure. The results obtained by on-chip interconnect capacitance equations and delay model are in excellent agreement with those by a field solver and circuit simulator, respectively. We also show that the model is very useful for evaluating effects of the process and design parameters on vertical signal propagation delay such as the sensitivity and variability analysis.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.2614/_p
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@ARTICLE{e98-a_12_2614,
author={Nanako NIIOKA, Masayuki WATANABE, Masa-aki FUKASE, Masashi IMAI, Atsushi KUROKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Signal Propagation Delay Model in Vertically Stacked Chips},
year={2015},
volume={E98-A},
number={12},
pages={2614-2624},
abstract={To design high quality three-dimensional integrated circuits (3-D ICs), the effect of process and design parameters on delay must be adequately understood. This paper presents an electrical circuit model of an entire structure in through silicon via (TSV) based 3-D ICs with a new equation for on-chip interconnect capacitance and then proposes an effective model for evaluating signal propagation delay in vertically stacked chips. All electrical parameter values can be calculated by the closed-form equations without a field solver. The delay model is constructed with the first- or second-order function of each parameter to the delay obtained from a typical structure. The results obtained by on-chip interconnect capacitance equations and delay model are in excellent agreement with those by a field solver and circuit simulator, respectively. We also show that the model is very useful for evaluating effects of the process and design parameters on vertical signal propagation delay such as the sensitivity and variability analysis.},
keywords={},
doi={10.1587/transfun.E98.A.2614},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Signal Propagation Delay Model in Vertically Stacked Chips
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2614
EP - 2624
AU - Nanako NIIOKA
AU - Masayuki WATANABE
AU - Masa-aki FUKASE
AU - Masashi IMAI
AU - Atsushi KUROKAWA
PY - 2015
DO - 10.1587/transfun.E98.A.2614
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2015
AB - To design high quality three-dimensional integrated circuits (3-D ICs), the effect of process and design parameters on delay must be adequately understood. This paper presents an electrical circuit model of an entire structure in through silicon via (TSV) based 3-D ICs with a new equation for on-chip interconnect capacitance and then proposes an effective model for evaluating signal propagation delay in vertically stacked chips. All electrical parameter values can be calculated by the closed-form equations without a field solver. The delay model is constructed with the first- or second-order function of each parameter to the delay obtained from a typical structure. The results obtained by on-chip interconnect capacitance equations and delay model are in excellent agreement with those by a field solver and circuit simulator, respectively. We also show that the model is very useful for evaluating effects of the process and design parameters on vertical signal propagation delay such as the sensitivity and variability analysis.
ER -
English
