IEICE TRANSACTIONS on Fundamentals
VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems
Summary :
Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.3 pp.811-819
- Publication Date
- 2015/03/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.811
- Type of Manuscript
- PAPER
- Category
- Digital Signal Processing
Authors
Shingo YOSHIZAWA
Kitami Institute of Technology
Mai NOZAKI
Kitami Institute of Technology
Hiroshi TANIMOTO
Kitami Institute of Technology
Keyword
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Shingo YOSHIZAWA, Mai NOZAKI, Hiroshi TANIMOTO, "VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 3, pp. 811-819, March 2015, doi: 10.1587/transfun.E98.A.811.
Abstract: Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.811/_p
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@ARTICLE{e98-a_3_811,
author={Shingo YOSHIZAWA, Mai NOZAKI, Hiroshi TANIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems},
year={2015},
volume={E98-A},
number={3},
pages={811-819},
abstract={Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition.},
keywords={},
doi={10.1587/transfun.E98.A.811},
ISSN={1745-1337},
month={March},}
Copy
TY - JOUR
TI - VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 811
EP - 819
AU - Shingo YOSHIZAWA
AU - Mai NOZAKI
AU - Hiroshi TANIMOTO
PY - 2015
DO - 10.1587/transfun.E98.A.811
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2015
AB - Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition.
ER -
English
