IEICE TRANSACTIONS on Fundamentals
The ASIC Implementation of SM3 Hash Algorithm for High Throughput
Summary :
SM3 is a hash function standard defined by China. Unlike SHA-1 and SHA-2, it is hard for SM3 to speed up the throughput because it has more complicated compression function than other hash algorithm. In this paper, we propose a 4-round-in-1 structure to reduce the number of rounds, and a logical simplifying to move 3 adders and 3 XOR gates from critical path to the non-critical path. Based in SMIC 65nm CMOS technology, the throughput of SM3 can achieve 6.54Gbps which is higher than that of the reported designs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.7 pp.1481-1487
- Publication Date
- 2016/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.1481
- Type of Manuscript
- LETTER
- Category
- Cryptography and Information Security
Authors
Xiaojing DU
Tsinghua University
Shuguo LI
Tsinghua University
Keyword
Latest Issue
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Xiaojing DU, Shuguo LI, "The ASIC Implementation of SM3 Hash Algorithm for High Throughput" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 7, pp. 1481-1487, July 2016, doi: 10.1587/transfun.E99.A.1481.
Abstract: SM3 is a hash function standard defined by China. Unlike SHA-1 and SHA-2, it is hard for SM3 to speed up the throughput because it has more complicated compression function than other hash algorithm. In this paper, we propose a 4-round-in-1 structure to reduce the number of rounds, and a logical simplifying to move 3 adders and 3 XOR gates from critical path to the non-critical path. Based in SMIC 65nm CMOS technology, the throughput of SM3 can achieve 6.54Gbps which is higher than that of the reported designs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1481/_p
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@ARTICLE{e99-a_7_1481,
author={Xiaojing DU, Shuguo LI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={The ASIC Implementation of SM3 Hash Algorithm for High Throughput},
year={2016},
volume={E99-A},
number={7},
pages={1481-1487},
abstract={SM3 is a hash function standard defined by China. Unlike SHA-1 and SHA-2, it is hard for SM3 to speed up the throughput because it has more complicated compression function than other hash algorithm. In this paper, we propose a 4-round-in-1 structure to reduce the number of rounds, and a logical simplifying to move 3 adders and 3 XOR gates from critical path to the non-critical path. Based in SMIC 65nm CMOS technology, the throughput of SM3 can achieve 6.54Gbps which is higher than that of the reported designs.},
keywords={},
doi={10.1587/transfun.E99.A.1481},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - The ASIC Implementation of SM3 Hash Algorithm for High Throughput
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1481
EP - 1487
AU - Xiaojing DU
AU - Shuguo LI
PY - 2016
DO - 10.1587/transfun.E99.A.1481
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2016
AB - SM3 is a hash function standard defined by China. Unlike SHA-1 and SHA-2, it is hard for SM3 to speed up the throughput because it has more complicated compression function than other hash algorithm. In this paper, we propose a 4-round-in-1 structure to reduce the number of rounds, and a logical simplifying to move 3 adders and 3 XOR gates from critical path to the non-critical path. Based in SMIC 65nm CMOS technology, the throughput of SM3 can achieve 6.54Gbps which is higher than that of the reported designs.
ER -
English
