In this paper, a new digital true random number generator based on Cross Feedback Ring Oscillators (CFRO) is proposed. The random sources of CFRO lie in delay variations (jitter), unpredictable transition behaviors as well as metastability. The CFRO is proved to be truly random by restarting from the same initial states. Compared with the so-called Fibonacci Ring Oscillator (FIRO) and Galois Ring Oscillator (GARO), the CFRO needs less than half of their time to accumulate relatively high entropy and enable extraction of one random bit. Only a simple XOR corrector is used to reduce the bias of output sequences. TRNG based on CFRO can be run continuously at a constant high speed of 150Mbps. For higher security, the TRNG can be set in stateless mode at a cost of slower speed of 10Mbps. The total logical resources used are relatively small and no special placement and routing is needed. The TRNG both in continuous mode and in stateless mode can pass the NIST tests and the DIEHARD tests.

In this paper, we propose a true random number generator (TRNG) exploiting jitter and the chaotic behavior in cross ring oscillators (CROs). We make a further study of the feedback ring architecture and cross-connect the XOR gates and inverters to form an oscillator. The CRO utilizes totally digital logic circuits, and gains a high and robust entropy rate, as the jitter in the CRO can accumulate locally between adjacent stages. Two specific working modes of CRO in which the CRO can work in a consistent state and a free-running state respectively are introduced and analyzed both theoretically and experimentally. Finally, different stage lengths of cross ring true random number generators (CRTRNGs) are tested in different Field Programmable Gate Arrays (FPGAs) and test results are analyzed and compared. Especially, random data achieved from a design of 63-stage CRTRNG in Altera Cyclone IV passes both the NIST and Diehard test suites at a rate as high as 240Mbit/s.

Field Programmable Gate Array (FPGA) implementation of Elliptic Curve Cryptography (ECC) over GF(p) is commonly not fast enough to meet the request of high-performance applications. There are three critical factors to determine the performance of ECC processor over GF(p): multiplication structure, modular multiplication algorithm, and scalar point multiplication scheduling. This work proposes a novel multiplication structure which is a two-stage pipeline on the basis of Karatsuba-Ofman algorithm. With the proposed multiplication structure, we design a 256-bit modular multiplier based on Improved Barret Modular Multiplication algorithm. Upon the modular multiplier, we finish the scalar point multiplication scheduling and implement a high-performance ECC processor on FPGA. Compared with the previous modular multipliers, our modular multiplier reduces the 256-bit modular multiplication time by 28% at least. Synthesis result on Altera Stratix II shows that our ECC processor can complete a 256-bit ECC scalar point multiplication in 0.51ms, which is at least 1.3 times faster than the currently reported FPGA ECC processors over GF(p).

SM3 is a hash function standard defined by China. Unlike SHA-1 and SHA-2, it is hard for SM3 to speed up the throughput because it has more complicated compression function than other hash algorithm. In this paper, we propose a 4-round-in-1 structure to reduce the number of rounds, and a logical simplifying to move 3 adders and 3 XOR gates from critical path to the non-critical path. Based in SMIC 65nm CMOS technology, the throughput of SM3 can achieve 6.54Gbps which is higher than that of the reported designs.