IEICE TRANSACTIONS on Fundamentals
A Test Pattern Compaction Method Using SAT-Based Fault Grouping
Summary :
This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2302-2309
- Publication Date
- 2016/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.2302
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Yusuke MATSUNAGA
Kyushu University
Keyword
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Yusuke MATSUNAGA, "A Test Pattern Compaction Method Using SAT-Based Fault Grouping" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 12, pp. 2302-2309, December 2016, doi: 10.1587/transfun.E99.A.2302.
Abstract: This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2302/_p
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@ARTICLE{e99-a_12_2302,
author={Yusuke MATSUNAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Test Pattern Compaction Method Using SAT-Based Fault Grouping},
year={2016},
volume={E99-A},
number={12},
pages={2302-2309},
abstract={This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.},
keywords={},
doi={10.1587/transfun.E99.A.2302},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Test Pattern Compaction Method Using SAT-Based Fault Grouping
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2302
EP - 2309
AU - Yusuke MATSUNAGA
PY - 2016
DO - 10.1587/transfun.E99.A.2302
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.
ER -
English
