IEICE TRANSACTIONS on Information
Delay Fault Testing of Processor Cores in Functional Mode
Summary :
This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.3 pp.610-618
- Publication Date
- 2005/03/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.3.610
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Virendra SINGH, Michiko INOUE, Kewal K. SALUJA, Hideo FUJIWARA, "Delay Fault Testing of Processor Cores in Functional Mode" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 3, pp. 610-618, March 2005, doi: 10.1093/ietisy/e88-d.3.610.
Abstract: This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.3.610/_p
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@ARTICLE{e88-d_3_610,
author={Virendra SINGH, Michiko INOUE, Kewal K. SALUJA, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Delay Fault Testing of Processor Cores in Functional Mode},
year={2005},
volume={E88-D},
number={3},
pages={610-618},
abstract={This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.},
keywords={},
doi={10.1093/ietisy/e88-d.3.610},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - Delay Fault Testing of Processor Cores in Functional Mode
T2 - IEICE TRANSACTIONS on Information
SP - 610
EP - 618
AU - Virendra SINGH
AU - Michiko INOUE
AU - Kewal K. SALUJA
AU - Hideo FUJIWARA
PY - 2005
DO - 10.1093/ietisy/e88-d.3.610
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2005
AB - This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.
ER -
English
