IEICE TRANSACTIONS on Information
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
Summary :
In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.9 pp.2135-2142
- Publication Date
- 2005/09/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.9.2135
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Kazuteru NAMBA, Hideo ITO, "Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 9, pp. 2135-2142, September 2005, doi: 10.1093/ietisy/e88-d.9.2135.
Abstract: In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.9.2135/_p
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@ARTICLE{e88-d_9_2135,
author={Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation},
year={2005},
volume={E88-D},
number={9},
pages={2135-2142},
abstract={In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.},
keywords={},
doi={10.1093/ietisy/e88-d.9.2135},
ISSN={},
month={September},}
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TY - JOUR
TI - Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
T2 - IEICE TRANSACTIONS on Information
SP - 2135
EP - 2142
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2005
DO - 10.1093/ietisy/e88-d.9.2135
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2005
AB - In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.
ER -
English
