Redundant Design for Wallace Multiplier

Kazuteru NAMBA, Hideo ITO

Summary :

To increase the yield of data processing circuits such as adders and logic operation circuits, the bit-slice reconfiguration design has been proposed as an efficient redundant technology for defect-tolerance. Wallace multipliers are a well-known class of high-speed parallel multipliers. Unfortunately, the bit-slice reconfiguration design is not applicable to Wallace multipliers because Wallace multipliers do not have regular bit-slice structure. Therefore, redundant designs for Wallace multipliers have been regarded impossible. This paper proposes a redundant design for Wallace multipliers. In order to design redundant Wallace multipliers, first, 2n heterogeneous slices are considered in a non-redundant nn Wallace multiplier. The proposed redundant Wallace multipliers contain reconfigurable slices which can play the role of both i-th and (i+1)-th slices. Since the i-th slice has a similar structure to the (i+1)-th slice, the reconfigurable slice is not much larger than the i-th slice. This paper also shows a repair procedure for the proposed design. This paper evaluates the proposed design from the viewpoint of the yield, area, effective yield and delay time. For example, the yield of a 3232 Wallace multiplier increases from 0.30 to 0.41 by applying the proposed design while the area increases by a factor of 1.21.

• Publication: IEICE TRANSACTIONS on Information Vol.E89-D No.9 pp.2512-2524
• Publication Date: 2006/09/01
• Online ISSN: 1745-1361
• DOI: 10.1093/ietisy/e89-d.9.2512
• Type of Manuscript: PAPER
• Category: Dependable Computing

Authors

Kazuteru NAMBA
Hideo ITO

Keyword

Wallace multiplier,  bit-slice reconfiguration redundant design,  defect-tolerance,  yield