IEICE TRANSACTIONS on Information
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
Summary :
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology including two-surface layout, it does not affect the design of the other layer, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the none temporal correlation algorithm suffers from 30% performance loss.
- Publication
- IEICE TRANSACTIONS on Information Vol.E90-D No.12 pp.1914-1922
- Publication Date
- 2007/12/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e90-d.12.1914
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Reconfigurable System and Applications
Authors
Keyword
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Daihan WANG, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, "A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs" in IEICE TRANSACTIONS on Information,
vol. E90-D, no. 12, pp. 1914-1922, December 2007, doi: 10.1093/ietisy/e90-d.12.1914.
Abstract: A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology including two-surface layout, it does not affect the design of the other layer, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the none temporal correlation algorithm suffers from 30% performance loss.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.12.1914/_p
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@ARTICLE{e90-d_12_1914,
author={Daihan WANG, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs},
year={2007},
volume={E90-D},
number={12},
pages={1914-1922},
abstract={A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology including two-surface layout, it does not affect the design of the other layer, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the none temporal correlation algorithm suffers from 30% performance loss.},
keywords={},
doi={10.1093/ietisy/e90-d.12.1914},
ISSN={1745-1361},
month={December},}
Copy
TY - JOUR
TI - A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 1914
EP - 1922
AU - Daihan WANG
AU - Hiroki MATSUTANI
AU - Michihiro KOIBUCHI
AU - Hideharu AMANO
PY - 2007
DO - 10.1093/ietisy/e90-d.12.1914
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2007
AB - A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology including two-surface layout, it does not affect the design of the other layer, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the none temporal correlation algorithm suffers from 30% performance loss.
ER -
English
