Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ<SUP><I>k</I></SUP>-Notation

Chia Yee OOI; Thomas CLOUQUEUR; Hideo FUJIWARA

doi:10.1093/ietisy/e90-d.8.1202

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation

Chia Yee OOI, Thomas CLOUQUEUR, Hideo FUJIWARA

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In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τ^k-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.

Publication: IEICE TRANSACTIONS on Information Vol.E90-D No.8 pp.1202-1212

Publication Date: 2007/08/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1093/ietisy/e90-d.8.1202

Type of Manuscript: PAPER

Category: Complexity Theory

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Chia Yee OOI, Thomas CLOUQUEUR, Hideo FUJIWARA, "Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation" in IEICE TRANSACTIONS on Information, vol. E90-D, no. 8, pp. 1202-1212, August 2007, doi: 10.1093/ietisy/e90-d.8.1202.
Abstract: In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τ^k-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.8.1202/_p

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@ARTICLE{e90-d_8_1202,
author={Chia Yee OOI, Thomas CLOUQUEUR, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation},
year={2007},
volume={E90-D},
number={8},
pages={1202-1212},
abstract={In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τ^k-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.},
keywords={},
doi={10.1093/ietisy/e90-d.8.1202},
ISSN={1745-1361},
month={August},}

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TY - JOUR
TI - Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation
T2 - IEICE TRANSACTIONS on Information
SP - 1202
EP - 1212
AU - Chia Yee OOI
AU - Thomas CLOUQUEUR
AU - Hideo FUJIWARA
PY - 2007
DO - 10.1093/ietisy/e90-d.8.1202
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2007
AB - In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τ^k-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.
ER -