IEICE TRANSACTIONS on Information
Memory Allocation for Multi-Resolution Image Processing
Summary :
Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.
- Publication
- IEICE TRANSACTIONS on Information Vol.E91-D No.10 pp.2386-2397
- Publication Date
- 2008/10/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e91-d.10.2386
- Type of Manuscript
- PAPER
- Category
- VLSI Systems
Authors
Keyword
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Yasuhiro KOBAYASHI, Masanori HARIYAMA, Michitaka KAMEYAMA, "Memory Allocation for Multi-Resolution Image Processing" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 10, pp. 2386-2397, October 2008, doi: 10.1093/ietisy/e91-d.10.2386.
Abstract: Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.10.2386/_p
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@ARTICLE{e91-d_10_2386,
author={Yasuhiro KOBAYASHI, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Information},
title={Memory Allocation for Multi-Resolution Image Processing},
year={2008},
volume={E91-D},
number={10},
pages={2386-2397},
abstract={Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.},
keywords={},
doi={10.1093/ietisy/e91-d.10.2386},
ISSN={1745-1361},
month={October},}
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TY - JOUR
TI - Memory Allocation for Multi-Resolution Image Processing
T2 - IEICE TRANSACTIONS on Information
SP - 2386
EP - 2397
AU - Yasuhiro KOBAYASHI
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2008
DO - 10.1093/ietisy/e91-d.10.2386
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2008
AB - Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.
ER -
English
