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Memory Allocation for Multi-Resolution Image Processing

Yasuhiro KOBAYASHI, Masanori HARIYAMA, Michitaka KAMEYAMA

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Summary :

Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.

Publication
IEICE TRANSACTIONS on Information Vol.E91-D No.10 pp.2386-2397
Publication Date
2008/10/01
Publicized
Online ISSN
1745-1361
DOI
10.1093/ietisy/e91-d.10.2386
Type of Manuscript
PAPER
Category
VLSI Systems

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