Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs
Summary :
MISRs are widely used as signature circuits for VLSI built-in self tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is grater than m. The aliasing probability as a function of the test length is analyzed for the compaction circuits for a binary symmetric channel. It is observed that the peak aliasing probability of the double MISRs is less than that of M-stage MISRs with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2
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- IEICE TRANSACTIONS on Information Vol.E75-D No.6 pp.835-841
- Publication Date
- 1992/11/25
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- Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
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Kazuhiko IWASAKI, Shou-Ping FENG, Toru FUJIWARA, Tadao KASAMI, "Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs" in IEICE TRANSACTIONS on Information,
vol. E75-D, no. 6, pp. 835-841, November 1992, doi: .
Abstract: MISRs are widely used as signature circuits for VLSI built-in self tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is grater than m. The aliasing probability as a function of the test length is analyzed for the compaction circuits for a binary symmetric channel. It is observed that the peak aliasing probability of the double MISRs is less than that of M-stage MISRs with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2
URL: https://global.ieice.org/en_transactions/information/10.1587/e75-d_6_835/_p
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@ARTICLE{e75-d_6_835,
author={Kazuhiko IWASAKI, Shou-Ping FENG, Toru FUJIWARA, Tadao KASAMI, },
journal={IEICE TRANSACTIONS on Information},
title={Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs},
year={1992},
volume={E75-D},
number={6},
pages={835-841},
abstract={MISRs are widely used as signature circuits for VLSI built-in self tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is grater than m. The aliasing probability as a function of the test length is analyzed for the compaction circuits for a binary symmetric channel. It is observed that the peak aliasing probability of the double MISRs is less than that of M-stage MISRs with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs
T2 - IEICE TRANSACTIONS on Information
SP - 835
EP - 841
AU - Kazuhiko IWASAKI
AU - Shou-Ping FENG
AU - Toru FUJIWARA
AU - Tadao KASAMI
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E75-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - November 1992
AB - MISRs are widely used as signature circuits for VLSI built-in self tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is grater than m. The aliasing probability as a function of the test length is analyzed for the compaction circuits for a binary symmetric channel. It is observed that the peak aliasing probability of the double MISRs is less than that of M-stage MISRs with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2
ER -
English
