A Concurrent Fault Detection Method for Instruction Level Parallel Processors

Alberto PALACIOS PAWLOVSKY; Makoto HANAWA

A Concurrent Fault Detection Method for Instruction Level Parallel Processors

Alberto PALACIOS PAWLOVSKY, Makoto HANAWA

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This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.

Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.7 pp.755-762

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design)

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Alberto PALACIOS PAWLOVSKY, Makoto HANAWA, "A Concurrent Fault Detection Method for Instruction Level Parallel Processors" in IEICE TRANSACTIONS on Information, vol. E76-D, no. 7, pp. 755-762, July 1993, doi: .
Abstract: This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_7_755/_p

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@ARTICLE{e76-d_7_755,
author={Alberto PALACIOS PAWLOVSKY, Makoto HANAWA, },
journal={IEICE TRANSACTIONS on Information},
title={A Concurrent Fault Detection Method for Instruction Level Parallel Processors},
year={1993},
volume={E76-D},
number={7},
pages={755-762},
abstract={This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A Concurrent Fault Detection Method for Instruction Level Parallel Processors
T2 - IEICE TRANSACTIONS on Information
SP - 755
EP - 762
AU - Alberto PALACIOS PAWLOVSKY
AU - Makoto HANAWA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1993
AB - This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.
ER -