High-Level Modeling and Synthesis of Communicating Processes Using VHDL
Summary :
The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.
- Publication
- IEICE TRANSACTIONS on Information Vol.E76-D No.9 pp.1039-1046
- Publication Date
- 1993/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
- Category
- High-Level Design
Authors
Keyword
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Wayne WOLF, Richard MANNO, "High-Level Modeling and Synthesis of Communicating Processes Using VHDL" in IEICE TRANSACTIONS on Information,
vol. E76-D, no. 9, pp. 1039-1046, September 1993, doi: .
Abstract: The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_9_1039/_p
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@ARTICLE{e76-d_9_1039,
author={Wayne WOLF, Richard MANNO, },
journal={IEICE TRANSACTIONS on Information},
title={High-Level Modeling and Synthesis of Communicating Processes Using VHDL},
year={1993},
volume={E76-D},
number={9},
pages={1039-1046},
abstract={The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.},
keywords={},
doi={},
ISSN={},
month={September},}
Copy
TY - JOUR
TI - High-Level Modeling and Synthesis of Communicating Processes Using VHDL
T2 - IEICE TRANSACTIONS on Information
SP - 1039
EP - 1046
AU - Wayne WOLF
AU - Richard MANNO
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1993
AB - The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.
ER -
English
