VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis

P. N. SANKARSHANAN; Hideaki KOBAYASHI; Pankaj KUKKAL; Hiroyuki KANBARA

VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis

P. N. SANKARSHANAN, Hideaki KOBAYASHI, Pankaj KUKKAL, Hiroyuki KANBARA

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This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.

Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.9 pp.1055-1065

Publication Date: 1993/09/25

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Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: Hardware Design Languages

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P. N. SANKARSHANAN, Hideaki KOBAYASHI, Pankaj KUKKAL, Hiroyuki KANBARA, "VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis" in IEICE TRANSACTIONS on Information, vol. E76-D, no. 9, pp. 1055-1065, September 1993, doi: .
Abstract: This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_9_1055/_p

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@ARTICLE{e76-d_9_1055,
author={P. N. SANKARSHANAN, Hideaki KOBAYASHI, Pankaj KUKKAL, Hiroyuki KANBARA, },
journal={IEICE TRANSACTIONS on Information},
title={VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis},
year={1993},
volume={E76-D},
number={9},
pages={1055-1065},
abstract={This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis
T2 - IEICE TRANSACTIONS on Information
SP - 1055
EP - 1065
AU - P. N. SANKARSHANAN
AU - Hideaki KOBAYASHI
AU - Pankaj KUKKAL
AU - Hiroyuki KANBARA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1993
AB - This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.
ER -