IEICE TRANSACTIONS on Information
Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams
Summary :
In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O (n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O (log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input 2-rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.
- Publication
- IEICE TRANSACTIONS on Information Vol.E76-D No.9 pp.1085-1092
- Publication Date
- 1993/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
- Category
- Logic Synthesis
Authors
Keyword
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Nagisa ISHIURA, "Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams" in IEICE TRANSACTIONS on Information,
vol. E76-D, no. 9, pp. 1085-1092, September 1993, doi: .
Abstract: In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O (n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O (log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input 2-rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_9_1085/_p
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@ARTICLE{e76-d_9_1085,
author={Nagisa ISHIURA, },
journal={IEICE TRANSACTIONS on Information},
title={Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams},
year={1993},
volume={E76-D},
number={9},
pages={1085-1092},
abstract={In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O (n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O (log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input 2-rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams
T2 - IEICE TRANSACTIONS on Information
SP - 1085
EP - 1092
AU - Nagisa ISHIURA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1993
AB - In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O (n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O (log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input 2-rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.
ER -
English
