Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel
Summary :
A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.
- Publication
- IEICE TRANSACTIONS on Information Vol.E79-D No.4 pp.297-305
- Publication Date
- 1996/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Computer Hardware and Design
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Woo-Chan PARK, Shi-Wha LEE, Oh-Young KWON, Tack-Don HAN, Shin-Dug KIM, "Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel" in IEICE TRANSACTIONS on Information,
vol. E79-D, no. 4, pp. 297-305, April 1996, doi: .
Abstract: A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.
URL: https://global.ieice.org/en_transactions/information/10.1587/e79-d_4_297/_p
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@ARTICLE{e79-d_4_297,
author={Woo-Chan PARK, Shi-Wha LEE, Oh-Young KWON, Tack-Don HAN, Shin-Dug KIM, },
journal={IEICE TRANSACTIONS on Information},
title={Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel},
year={1996},
volume={E79-D},
number={4},
pages={297-305},
abstract={A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel
T2 - IEICE TRANSACTIONS on Information
SP - 297
EP - 305
AU - Woo-Chan PARK
AU - Shi-Wha LEE
AU - Oh-Young KWON
AU - Tack-Don HAN
AU - Shin-Dug KIM
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E79-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 1996
AB - A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.
ER -
English
