Flexible VLSI Architecture for Block-Matching Motion Estimation
Summary :
Full-search block-matching motion estimation is a popular method to reduce temporal redundancies in video sequence. Due to its excessive computational load, parallel processing architectures are often required for real-time processing. One of the architectures is Hsieh's architecture based on systolic array processor and shift register arrays. Serial input characteristic of his scheme can reduce the number of pixel inputs to one, at the expense of significantly increasing the initialization time. This paper presents a modified and generalized Hsieh's architecture to reduce the initialization time. The proposed architecture can easily control data flows by rearranging shift register arrays and input-pin counts by using multiplexers on input stage, while retaining good properties of Hsieh's. The proposed architecture has the following advantages: (1) it allows controllable data inputs to save the pin counts, (2) it is flexible to the dimensional change of the search area via simple control, (3) it can operate in real time for video conference applications, and (4) it has simple and modular structure which is quite suitable for VLSI implementation. For verification of the proposed architecture, VHDL simulations are performed and some results are given.
- Publication
- IEICE TRANSACTIONS on Information Vol.E79-D No.6 pp.752-758
- Publication Date
- 1996/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Multimedia Computing and Communications)
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Han-Kyu LEE, Jae-Yeal NAM, Jin-Soo CHOI, Yeong-Ho HA, "Flexible VLSI Architecture for Block-Matching Motion Estimation" in IEICE TRANSACTIONS on Information,
vol. E79-D, no. 6, pp. 752-758, June 1996, doi: .
Abstract: Full-search block-matching motion estimation is a popular method to reduce temporal redundancies in video sequence. Due to its excessive computational load, parallel processing architectures are often required for real-time processing. One of the architectures is Hsieh's architecture based on systolic array processor and shift register arrays. Serial input characteristic of his scheme can reduce the number of pixel inputs to one, at the expense of significantly increasing the initialization time. This paper presents a modified and generalized Hsieh's architecture to reduce the initialization time. The proposed architecture can easily control data flows by rearranging shift register arrays and input-pin counts by using multiplexers on input stage, while retaining good properties of Hsieh's. The proposed architecture has the following advantages: (1) it allows controllable data inputs to save the pin counts, (2) it is flexible to the dimensional change of the search area via simple control, (3) it can operate in real time for video conference applications, and (4) it has simple and modular structure which is quite suitable for VLSI implementation. For verification of the proposed architecture, VHDL simulations are performed and some results are given.
URL: https://global.ieice.org/en_transactions/information/10.1587/e79-d_6_752/_p
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@ARTICLE{e79-d_6_752,
author={Han-Kyu LEE, Jae-Yeal NAM, Jin-Soo CHOI, Yeong-Ho HA, },
journal={IEICE TRANSACTIONS on Information},
title={Flexible VLSI Architecture for Block-Matching Motion Estimation},
year={1996},
volume={E79-D},
number={6},
pages={752-758},
abstract={Full-search block-matching motion estimation is a popular method to reduce temporal redundancies in video sequence. Due to its excessive computational load, parallel processing architectures are often required for real-time processing. One of the architectures is Hsieh's architecture based on systolic array processor and shift register arrays. Serial input characteristic of his scheme can reduce the number of pixel inputs to one, at the expense of significantly increasing the initialization time. This paper presents a modified and generalized Hsieh's architecture to reduce the initialization time. The proposed architecture can easily control data flows by rearranging shift register arrays and input-pin counts by using multiplexers on input stage, while retaining good properties of Hsieh's. The proposed architecture has the following advantages: (1) it allows controllable data inputs to save the pin counts, (2) it is flexible to the dimensional change of the search area via simple control, (3) it can operate in real time for video conference applications, and (4) it has simple and modular structure which is quite suitable for VLSI implementation. For verification of the proposed architecture, VHDL simulations are performed and some results are given.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Flexible VLSI Architecture for Block-Matching Motion Estimation
T2 - IEICE TRANSACTIONS on Information
SP - 752
EP - 758
AU - Han-Kyu LEE
AU - Jae-Yeal NAM
AU - Jin-Soo CHOI
AU - Yeong-Ho HA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E79-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 1996
AB - Full-search block-matching motion estimation is a popular method to reduce temporal redundancies in video sequence. Due to its excessive computational load, parallel processing architectures are often required for real-time processing. One of the architectures is Hsieh's architecture based on systolic array processor and shift register arrays. Serial input characteristic of his scheme can reduce the number of pixel inputs to one, at the expense of significantly increasing the initialization time. This paper presents a modified and generalized Hsieh's architecture to reduce the initialization time. The proposed architecture can easily control data flows by rearranging shift register arrays and input-pin counts by using multiplexers on input stage, while retaining good properties of Hsieh's. The proposed architecture has the following advantages: (1) it allows controllable data inputs to save the pin counts, (2) it is flexible to the dimensional change of the search area via simple control, (3) it can operate in real time for video conference applications, and (4) it has simple and modular structure which is quite suitable for VLSI implementation. For verification of the proposed architecture, VHDL simulations are performed and some results are given.
ER -
English
