The search functionality is under construction.
The search functionality is under construction.

Author Search Result

[Author] Jin-Soo CHOI(2hit)

1-2hit
  • Flexible VLSI Architecture for Block-Matching Motion Estimation

    Han-Kyu LEE  Jae-Yeal NAM  Jin-Soo CHOI  Yeong-Ho HA  

     
    PAPER

      Vol:
    E79-D No:6
      Page(s):
    752-758

    Full-search block-matching motion estimation is a popular method to reduce temporal redundancies in video sequence. Due to its excessive computational load, parallel processing architectures are often required for real-time processing. One of the architectures is Hsieh's architecture based on systolic array processor and shift register arrays. Serial input characteristic of his scheme can reduce the number of pixel inputs to one, at the expense of significantly increasing the initialization time. This paper presents a modified and generalized Hsieh's architecture to reduce the initialization time. The proposed architecture can easily control data flows by rearranging shift register arrays and input-pin counts by using multiplexers on input stage, while retaining good properties of Hsieh's. The proposed architecture has the following advantages: (1) it allows controllable data inputs to save the pin counts, (2) it is flexible to the dimensional change of the search area via simple control, (3) it can operate in real time for video conference applications, and (4) it has simple and modular structure which is quite suitable for VLSI implementation. For verification of the proposed architecture, VHDL simulations are performed and some results are given.

  • Selective Epitaxial Growth of SiGe Layers with High Aspect Ratio Mask of Dielectric Films

    A-Ram CHOI  Sang-Sik CHOI  Byung-Guan PARK  Dongwoo SUH  Gyungock KIM  Jin-Tae KIM  Jin-Soo CHOI  Deok-Ho CHO  Tae-Hyun HAN  Kyu-Hwan SHIM  

     
    PAPER

      Vol:
    E91-C No:5
      Page(s):
    767-771

    This paper presents the selective epitaxial growth (SEG) properties of reduced pressure chemical vapor deposition (RPCVD) at low temperatures (LT) of 675-725 with high aspect ratio mask of dielectric films. The SEG process could be explained in conjunction with the loading effect, the mask pattern shape/size, and the process parameters of RPCVD. The growth rates showed a large non-uniformity up to 40% depending upon the pattern size of the dielectric mask films, but as the SEG film becomes thicker, the growth rate difference converged on 15% between the narrow 2-µm and the wide 100-µm patterns. The evolution of SEG was controlled dominantly by the surface migration control at the initial stage, and converted to the surface topology control. The design of pattern size and distribution with dummy patterns must be useful to accomplish the reliable and uniform LT-SEG.