Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution

Hiroshi SAWADA; Takayuki SUYAMA; Akira NAGOYA

Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution

Hiroshi SAWADA, Takayuki SUYAMA, Akira NAGOYA

Full Text Views

0

Cite this

Summary :

This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.

Publication: IEICE TRANSACTIONS on Information Vol.E80-D No.10 pp.1017-1023

Publication Date: 1997/10/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: Logic Design

Cite this

Copy

Hiroshi SAWADA, Takayuki SUYAMA, Akira NAGOYA, "Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution" in IEICE TRANSACTIONS on Information, vol. E80-D, no. 10, pp. 1017-1023, October 1997, doi: .
Abstract: This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_10_1017/_p

Copy

@ARTICLE{e80-d_10_1017,
author={Hiroshi SAWADA, Takayuki SUYAMA, Akira NAGOYA, },
journal={IEICE TRANSACTIONS on Information},
title={Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution},
year={1997},
volume={E80-D},
number={10},
pages={1017-1023},
abstract={This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.},
keywords={},
doi={},
ISSN={},
month={October},}

Copy

TY - JOUR
TI - Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution
T2 - IEICE TRANSACTIONS on Information
SP - 1017
EP - 1023
AU - Hiroshi SAWADA
AU - Takayuki SUYAMA
AU - Akira NAGOYA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1997
AB - This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.
ER -