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[Author] Takayuki SUYAMA(3hit)

1-3hit
  • Incremental Environmental Monitoring for Revealing the Ecology of Endangered Fish Open Access

    Yoshinari SHIRAI  Yasue KISHINO  Shin MIZUTANI  Yutaka YANAGISAWA  Takayuki SUYAMA  Takuma OTSUKA  Tadao KITAGAWA  Futoshi NAYA  

     
    INVITED PAPER

      Pubricized:
    2018/04/13
      Vol:
    E101-B No:10
      Page(s):
    2070-2082

    This paper proposes a novel environmental monitoring strategy, incremental environmental monitoring, that enables scientists to reveal the ecology of wild animals in the field. We applied this strategy to the habitat of endangered freshwater fish. Specifically, we designed and implemented a network-based system using distributed sensors to continuously monitor and record the habitat of endangered fish. Moreover, we developed a set of analytical tools to exploit a variety of sensor data, including environmental time-series data such as amount of dissolved oxygen, as well as underwater video capturing the interaction of fish and their environment. We also describe the current state of monitoring the behavior and habitat of endangered fish and discuss solutions for making such environmental monitoring more efficient in the field.

  • A Network-Type Brain Machine Interface to Support Activities of Daily Living Open Access

    Takayuki SUYAMA  

     
    INVITED PAPER

      Vol:
    E99-B No:9
      Page(s):
    1930-1937

    To help elderly and physically disabled people to become self-reliant in daily life such as at home or a health clinic, we have developed a network-type brain machine interface (BMI) system called “network BMI” to control real-world actuators like wheelchairs based on human intention measured by a portable brain measurement system. In this paper, we introduce the technologies for achieving the network BMI system to support activities of daily living.

  • Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution

    Hiroshi SAWADA  Takayuki SUYAMA  Akira NAGOYA  

     
    PAPER-Logic Design

      Vol:
    E80-D No:10
      Page(s):
    1017-1023

    This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.